Sony Patent | Display Device, Method For Driving Display Device, And Electronic Device

Patent: Display Device, Method For Driving Display Device, And Electronic Device

Publication Number: 20200051505

Publication Date: 20200213

Applicants: Sony

Abstract

A display device according to the present disclosure includes: a pixel array unit (30) in which pixel circuits (20A) are disposed in a matrix form, the pixel circuits each including a light emission unit (21), a write transistor (23) that writes a signal voltage (Vsig) of a video signal, a retention capacitor (24) that retains the signal voltage (Vsig) written by the write transistor (23), a drive transistor (22) that drives the light emission unit (21) on the basis of the signal voltage (Vsig) retained by the retention capacitor (24), and an auxiliary capacitor (25) of which one terminal is connected to a source node of the drive transistor (22); and a control unit (90) that provides a potential change to a source electrode of the drive transistor (22) by coupling through the auxiliary capacitor (25) to set an operation point of the drive transistor (22) as a cut-off region after the threshold value correction process.

CROSS REFERENCES TO RELATED APPLICATIONS

[0001] The present application is a Continuation application of U.S. patent application Ser. No. 16/177,962 filed Nov. 1, 2018, which is a Continuation Application of U.S. patent application Ser. No. 15/510,461 filed Mar. 10, 2017, now U.S. Pat. No. 10,140,924 issued on Nov. 27, 2018, which is a 371 National Stage Entry of International Application No.: PCT/JP2015/074700, filed on Aug. 31, 2015, which in turn claims priority from Japanese Application No. 2014-224096, filed on Nov. 4, 2014, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

[0002] The present disclosure relates to a display device, a method for driving the display device, and an electronic device.

BACKGROUND ART

[0003] Recently, in the field of display devices, a flat panel type display device in which pixels (pixel circuits) including light emission units are 2-dimensionally disposed in a matrix form has become mainstream. In such a flat panel type display device, a characteristic of a transistor that drives a light emission unit may vary for each pixel due to a change in a process or the like. The characteristic variation of the transistor that drives the light emission unit affects light emitting luminance.

[0004] Specifically, even if a video signal of the same level (signal voltage) is written into each pixel, the light emitting luminance varies between pixels. Thus, display unevenness occurs, and then uniformity of a display screen deteriorates. Accordingly, a function for correcting the display unevenness due to the characteristic variation of the driving transistor that drives the light emission unit or the like is provided in the display device. Further, the correction operation is performed during a period in which a write transistor that writes a video signal is in a conductive state. The correction period in which the correction operation is performed is determined by a capacitance value of a pixel capacitor (capacity pixel).

[0005] However, in display devices having the above-described correction function, there are cases in which it is necessary to shorten a correction period (correction time) as a source voltage of the drive transistor varies during the correction operation. The correction period is determined by a pulse width of a drive pulse that drives the write transistor. Accordingly, it is possible to shorten the correction period by shortening the pulse width of the drive pulse. Thus, in the related art, a pulse width adjustment circuit is formed on a display panel to generate a pulse signal of which a pulse width is shortened on the basis of a pulse signal input from the outside, and the pulse signal is used as the drive pulse (for example, see PTL 1).

CITATION LIST

Patent Literature

[0006] Patent Literature 1: JP 2012-255875A

SUMMARY OF INVENTION

Technical Problem

[0007] However, according to the related art technology disclosed in PTL 1, since it is necessary for the pulse width adjustment circuit that generates the drive pulse of which the pulse width is shortened to be formed on the display panel, a circuit size of peripheral circuits that drive the pixel circuit increases. As a result, since the area of a peripheral circuit region of a pixel array unit on the display panel on which the peripheral circuits are disposed, that is, a so-called frame region, is increased, which hinders miniaturization of the display panel.

[0008] The present disclosure aims to provide a display device in which a pulse width of a drive pulse does not need to be shortened and in which a circuit size of peripheral circuits of a pixel array is enabled to be reduced, a method for driving the display device, and an electronic device including the display device.

Solution to Problem

[0009] To achieve the above described aim, a display device according to the present disclosure includes:

[0010] a pixel array unit in which pixel circuits are disposed in a matrix form, the pixel circuits each including a light emission unit, a write transistor that writes a signal voltage of a video signal, a retention capacitor that retains the signal voltage written by the write transistor, a drive transistor that drives the light emission unit on the basis of the signal voltage retained by the retention capacitor, and an auxiliary capacitor of which one terminal is connected to a source node of the drive transistor, the pixel circuit having a function of a threshold value correction process of changing a source voltage of the drive transistor toward a voltage obtained by subtracting a threshold value voltage of the drive transistor from an initialization voltage of a gate voltage of the drive transistor with reference to the initialization voltage;* and*

[0011] a control unit that provides a potential change to a source electrode of the drive transistor by coupling through the auxiliary capacitor to set an operation point of the drive transistor as a cut-off region after the threshold value correction process.

[0012] In addition, to achieve the above described aim, an electronic device according to the present disclosure includes the display device having the above described configuration.

[0013] To achieve the above described aim, according to the present disclosure, a method for driving a display device including a pixel array unit in which pixel circuits are disposed in a matrix form, the pixel circuits each including a light emission unit, a write transistor that writes a signal voltage of a video signal, a retention capacitor that retains the signal voltage written by the write transistor, a drive transistor that drives the light emission unit on the basis of the signal voltage retained by the retention capacitor, and an auxiliary capacitor of which one terminal is connected to a source node of the drive transistor, the pixel circuit having a function of a threshold value correction process of changing a source voltage of the drive transistor toward a voltage obtained by subtracting a threshold value voltage of the drive transistor from an initialization voltage of a gate voltage of the drive transistor with reference to the initialization voltage,* includes*

[0014] providing a potential change to a source electrode of the drive transistor by coupling through the auxiliary capacitor to set an operation point of the drive transistor as a cut-off region after the threshold value correction process, when driving the display device.

[0015] In the display device, the method for driving the display device and the electronic device having the above-described configurations, when the signal voltage is written by the write transistor, since the operation point of the drive transistor is the cut-off region, it is natural for a current not to flow into the drive transistor. Thus, it is possible to remove a factor that causes the source voltage of the drive transistor to fluctuate other than the coupling associated with the writing of the signal voltage. Accordingly, it is not necessary to shorten a correction period (correction time), and thus it is not necessary to narrow a pulse width of the drive pulse.

Advantageous Effects of Invention

[0016] According to the present disclosure, it is not necessary to shorten a pulse width of a drive pulse, and thus it is possible to reduce a circuit size of peripheral circuits of a pixel array.

[0017] Note that the present disclosure is not limited to exhibiting the effect described herein at all and may exhibit any effect described in the present specification. In addition, the effects described in the present specification are not limiting but are merely examples, and there may be additional effects.

BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a system configuration diagram showing an overview of a basic configuration of an active-matrix organic EL display device which is a premise of the present disclosure.

[0019] FIG. 2 is a circuit diagram showing a circuit configuration of a 2Tr2C unit pixel (pixel circuit).

[0020] FIG. 3 is a timing waveform diagram for describing a basic circuit operation in an ideal state of the active-matrix organic EL display device which is the premise of the present disclosure.

[0021] FIG. 4 is a waveform diagram illustrating a mobility correction operation, in which FIG. 4A shows an operation example in a case in which current supply capability of a drive transistor is large and a capacitance value of a pixel capacitor is small, and FIG. 4B shows an operation example of a case in which a mobility correction time is shortened.

[0022] FIG. 5 is a circuit diagram illustrating a configuration example of a pulse width adjustment circuit in a peripheral circuit of a pixel array unit.

[0023] FIG. 6 is a timing waveform diagram illustrating waveforms of signals of respective units in FIG. 5.

[0024] FIG. 7 is a system configuration diagram illustrating an overview of a configuration of an organic EL display device including pixel circuits according to Example 1.

[0025] FIG. 8 is a timing waveform diagram for describing a circuit operation of the organic EL display device including the pixel circuits according to Example 1.

[0026] FIG. 9 is a system configuration diagram illustrating an overview of a configuration of an organic EL display device including pixel circuits according to Example 2.

[0027] FIG. 10 is a timing waveform diagram for illustrating a circuit operation of the organic EL display device including the pixel circuits according to Example 2.

[0028] FIG. 11 is an external view of a lens interchangeable single lens reflex type digital camera, in which FIG. 11A is a front view thereof and FIG. 11B is a back view thereof.

[0029] FIG. 12 is an external view of a head mounted display.

MODE(S)* FOR CARRYING OUT THE INVENTION*

[0030] Hereinafter, preferred embodiments for implementing the technology of the present disclosure (which will be described hereinafter as “embodiments”) will be described in detail with reference to the appended drawings. The technology of the present disclosure is not limited to the embodiments, and the various numeric values and materials shown in the embodiments are examples. In description provided below, structural elements that have substantially the same function and structure are denoted with the same reference numerals, and repeated explanation of these structural elements is omitted. Note that description will be provided in the following order.

  1. Overall description of display device, method of driving display device, and electronic device of present disclosure 2. Display device which is premise of present disclosure 2-1. System configuration 2-2. Pixel circuit 2-3. Basic circuit operation in ideal state 2-4. Shortening of mobility correction time 2-5. Pulse width adjustment circuit 3. Display device according to embodiments of present disclosure 3-1. Example 1 (example in which pixel circuit is configured by N-channel type transistor) 3-2. Example 2 (example in which pixel circuit is configured by P-channel type transistor) 4. Electronic device 4-1. Specific example 1 (example of digital camera) 4-2. Specific example 2 (example of head mounted display)

<Overall Description of Display Device, Method for Driving Display Device, and Electronic Device of Present Disclosure>

[0031] In a display device, a method for driving the display device and an electronic device of the present disclosure, a configuration in which a control unit changes a potential of the source electrode of a drive transistor by providing a potential change to the other terminal of an auxiliary capacitor may be used. Further, when the other terminal of the auxiliary capacitor is connected to a control line, a configuration in which the control unit provides the potential change to the source electrode of the drive transistor by switching a control signal provided to the other terminal of the auxiliary capacitor through the control line from a non-active state to an active state may be used.

[0032] In the display device, the method for driving the display device and the electronic device of the present disclosure having the above-described preferable configurations, a configuration in which the source voltage of the drive transistor when the potential change is provided to the source electrode of the drive transistor is a voltage smaller than at least the sum of a cathode voltage of the light emission unit and a threshold value voltage of the light emission unit may be used. Further, a configuration in which the write transistor writes a signal voltage into the gate electrode of the drive transistor after the potential change is provided to the source electrode of the drive transistor may be used.

[0033] Further, in the display device, the method for driving the display device and the electronic device of the present disclosure having the above-described preferable configurations, a configuration including a write scanning unit that drives the write transistor through a scanning line in units of rows may be used. Here, it is preferable that the control unit and the write scanning unit be provided in a peripheral circuit region on the same side with respect to the pixel array unit. Further, it is preferable that the control line and the scanning line be formed of the same wire materials and to have the same thicknesses and widths.

[0034] Alternatively, in the display device, the method for driving the display device and the electronic device of the present disclosure having the above-described preferable configurations, a configuration in which, when entering an active state two times during the threshold value correction processing and the writing of the signal voltage, pulse widths of two pulses when the write scanning signal enters the active state two times are the same may be used. Further, a configuration in which the pixel circuit performs a mobility correction process in a period of the second pulse among the two pulses may be used. The mobility correction process is a process of correcting a mobility of the drive transistor by applying negative feedback to a potential difference between the gate electrode and the source electrode of the drive transistor by a correction amount corresponding to a current flowing in the drive transistor.

[System Configuration]

[0035] FIG. 1 is a system configuration diagram showing an overview of a basic configuration of an active-matrix organic EL display device which is a premise of the present disclosure.

[0036] The active-matrix display device is a display device in which driving of a light emission unit (light emission element) is performed by an active element provided in the same pixel as the light emission unit, for example, an insulated gate field-effect transistor. Typically, a thin film transistor (TFT) can be used as the insulated gate field-effect transistor.

[0037] Here, a case in which an active-matrix organic EL display device uses an organic EL element as a light emission unit (light emission element) of a unit pixel (pixel circuit) will be described as an example. The organic El element is a current-driven electro-optical element of which light emission luminance changes in accordance with to a value of a current flowing through the device. Hereinafter, the “unit pixel/pixel circuit” is described simply as a “pixel” in some cases. The thin film transistor is used not only for control of a pixel but also for control of a peripheral circuit to be described below.

[0038] As shown in FIG. 1, an active-matrix organic EL display device 10 which is a premise of the present disclosure is configured to include a pixel array unit 30 constituted such that a plurality of unit pixels 20 are disposed 2-dimensionally in a matrix form (matrix state), and a driving unit (peripheral circuit) disposed in a peripheral region of the pixel array unit 30 and driving the pixels 20. The driving unit is constituted by, for example, a write scanning unit 40, a power supply scanning unit 50, and a signal output unit 60 and drives the pixels 20 of the pixel array unit 30.

[0039] In this example, the write scanning unit 40, the power supply scanning unit 50, and the signal output unit 60 are mounted on the same substrate as the pixel array unit 30, that is, on a display panel 70, as peripheral circuits of the pixel array unit 30. However, a configuration in which some or all of the write scanning unit 40, the power supply scanning unit 50, and the signal output unit 60 are provided outside the display panel 70 may be employed. Further, a configuration in which the write scanning unit 40 and the power supply scanning unit 50 are both disposed on one side of the pixel array unit 30 is used, or a configuration in which the write scanning unit 40 and the power supply scanning unit 50 are disposed with the pixel array unit 30 interposed therebetween may be used. As a substrate of the display panel 70, a transparent insulating substrate such as a glass substrate may be used, or a semiconductor substrate such as a silicon substrate may be used.

[0040] Here, when the organic EL display device 10 performs color display, one pixel (unit pixel) serving as a unit when forming a color image is constituted by sub pixels in a plurality of colors. In this case, each of the sub pixels corresponds to a pixel 20 of FIG. 1. To be more specific, in the display device that performs color display, one pixel is constituted by, for example, three sub pixels including a sub pixel emitting red (R) light, a sub pixel emitting green (G) light, and a sub pixel emitting blue (B) light.

[0041] One pixel, however, is not limited to a combination of sub pixels having three primary colors including RGB, and it is also possible to add sub pixels having one or more colors to the sub pixels having the three primary colors to form one pixel. To be more specific, it is possible to form one pixel by adding a sub pixel that emits white (W) light to increase luminance, or to form one pixel by adding at least one sub pixel which emits a complementary color of light to expand a color reproduction range.

[0042] In the pixel array unit 30, scanning lines 31 (31.sub.1 to 31.sub.m) and power supply lines 32 (32.sub.1 to 32.sub.m) are wired for each pixel row in the row direction (pixel array direction of pixel rows or horizontal direction) in the array of the pixels 20 in m rows and n columns. Furthermore, signal lines 33 (33.sub.1 to 33.sub.n) are wired for each pixel column in the column direction (pixel array direction of pixel columns or vertical direction) in the array of the pixels 20 in m rows and n columns.

[0043] The scanning lines 31.sub.1 to 31.sub.m are connected to respective output terminals of the corresponding rows of the write scanning unit 40. The power supply lines 32.sub.1 to 32.sub.m are connected to respective output terminals of the corresponding rows of the power supply scanning unit 50. The signal lines 33.sub.1 to 33.sub.n are connected to output terminals of the corresponding columns of the signal output unit 60.

[0044] The write scanning unit 40 is constituted by a shift register circuit, and the like. At the time of writing a signal voltage of a video signal onto each pixel 20 of the pixel array unit 30, the write scanning unit 40 performs so-called line sequential scanning in which each of the pixels 20 of the pixel array unit 30 is sequentially scanned in units of rows by sequentially supplying write scanning signals WS (WS.sub.1 to WS.sub.m) to the scanning lines 31 (31.sub.1 to 31.sub.m).

[0045] The power supply scanning unit 50 is constituted by a shift register circuit and the like, like the write scanning unit 40. The power supply scanning unit 50 supplies power supply voltages DS (DS.sub.1 to DS.sub.m) that can be switched between a first power supply voltage V.sub.ccp and a second power supply voltage V.sub.ini that is lower than the first power supply voltage V.sub.ccp to the power supply lines 32 (32.sub.1 to 32.sub.m) in synchronization with the line sequential scanning performed by the write scanning unit 40. As will be described later, light emission and non-light emission (light-off) of the pixels 20 are controlled by the switching of the power supply voltages DS between V.sub.ccp and V.sub.ini.

[0046] The signal output unit 60 selectively outputs a signal voltage of a video signal (which may be described hereinafter simply as a “signal voltage”) V.sub.sig that is based on luminance information supplied from a signal supply source (not shown) and a reference voltage V.sub.ofs. Herein, the reference voltage V.sub.ofs is a voltage serving as a reference of the signal voltage of the video signal V.sub.sig (for example, a voltage equivalent to a black level of the video signal), and is used in a threshold value correction process to be described later.

[0047] The signal voltage V.sub.sig and the reference voltage V.sub.ofs output from the signal output unit 60 are written into each of the pixels 20 of the pixel array unit 30 via the signal lines 33 (33.sub.1 to 33.sub.n) in units of pixel rows selected through scanning performed by the write scanning unit 40. In other words, the signal output unit 60 employs a driving form of line sequential writing in which the signal voltage V.sub.sig is written in units of rows (lines).

[Pixel Circuit]

[0048] FIG. 2 is a circuit diagram showing an example of a detailed circuit configuration of a unit pixel (pixel circuit) 20. The light emission unit of the pixel 20 is constituted by an organic EL element 21 that is an example of a current-driven electro-optical element of which light emission luminance changes in accordance with a value of a current flowing through the device.

[0049] As shown in FIG. 2, the pixel 20 includes the organic EL element 21 and a drive circuit that drives the organic EL element 21 by applying a current to the organic EL element 21. The cathode electrode of the organic EL element 21 is connected to a common power supply line 34 that is commonly wired for all of the pixels 20.

[0050] The drive circuit that drives the organic EL element 21 has a 2Tr2C circuit configuration including a drive transistor 22, a writing transistor 23, a retention capacitor 24, and an auxiliary capacitor 25, that is, two transistors (Tr) and two capacitative elements (C). Here, N-channel type thin film transistors (TFTs) are used as the drive transistor 22 and the writing transistor 23. Here, a conductive combination of the drive transistor 22 and the writing transistor 23 mentioned here is merely an example, but the present disclosure is not limited to this combination.

[0051] One electrode (the source or drain electrode) of the drive transistor 22 is connected to each of the power supply lines 32 (32.sub.1 to 32.sub.m) and the other electrode (the source or drain electrode) thereof is connected to the anode electrode of the organic EL element 21. One electrode (the source or drain electrode) of the writing transistor 23 is connected to each of the signal lines 33 (33.sub.1 to 33.sub.m) and the other electrode (the source or the drain electrode) thereof is connected to the gate electrode of the drive transistor 22. In addition, the gate electrode of the writing transistor 23 is connected to each of the scanning lines 31 (31.sub.1 to 31.sub.m).

[0052] With regard to the drive transistor 22 and the writing transistor 23, one electrode refers to a metal wire electrically connected to one source or drain region, and the other electrode refers to a metal wire electrically connected to the other source or drain region. In addition, one electrode may be a source electrode or a drain electrode, and the other electrode may be a drain electrode or a source electrode in accordance with the electric potential relation between the one electrode and the other electrode.

[0053] One electrode of the retention capacitor 24 is connected to the gate electrode of the drive transistor 22, and the other electrode thereof is connected to the other electrode of the drive transistor 22 and to the anode electrode of the organic EL element 21. One electrode of the auxiliary capacitor 25 is connected to the anode electrode of the organic EL element 21 and the other electrode thereof is connected to the cathode electrode of the organic EL element 21. That is, the auxiliary capacitor 25 is connected in parallel to the organic EL element 21.

[0054] In the configuration described above, the writing transistor 23 enters a conductive state in which a state of a high voltage applied to the gate electrode thereof through the scanning line 31 from the write scanning unit 40 becomes an active state in response to the write scanning signal WS. Accordingly, the writing transistor 23 performs sampling on the signal voltage of the video signal V.sub.sig or the reference voltage V.sub.ofs according to luminance information supplied from the signal output unit 60 through the signal line 33 at different time points and writes the voltages into the pixel 20. The signal voltage V.sub.sig or the reference voltage V.sub.ofs written by the writing transistor 23 are retained by the retention capacitor 24.

[0055] When the power supply voltage DS of the power supply lines 32 (32.sub.1 to 32.sub.m) becomes the first power supply voltage V.sub.ccp, the drive transistor 22 operates in a saturation region as one electrode thereof serves as the drain electrode and the other electrode serves as the source electrode. Accordingly, the drive transistor 22 receives supply of a current from the power supply line 32 and then drives the organic EL element 21 to emit light through current driving. To be more specific, the drive transistor 22 supplies the driving current of a current value according to the voltage value of the signal voltage V.sub.sig retained in the retention capacitor 24 to the organic EL element 21 to drive the organic EL element 21 to emit light using the current.

[0056] Further, when the power supply voltage DS is switched from the first power supply voltage V.sub.ccp to the second power supply voltage V.sub.ini, the drive transistor 22 operates as a switching transistor as one electrode thereof serves as the source electrode and the other electrode thereof serves as the drain electrode. Accordingly, the drive transistor 22 stops the supply of the driving current to the organic EL element 21 thereby setting the organic EL element 21 to be in a non-light-emission state. In other words, the drive transistor 22 also has the function as a transistor which controls light emission and non-light-emission of the organic EL element 21.

[0057] Through the switching operation of the drive transistor 22, it is possible to set a period in which the organic EL element 21 is in a non-light-emission state (non-light-emission period) and to control a ratio of a light emission period and a non-light-emission period (duty) of the organic EL element 21. With the control of the duty, it is possible to reduce after image and blur caused by light emission of the pixel over one display frame period, and particularly, to make a level of quality of a dynamic image more preferable.

[0058] Among the first and second power supply voltages V.sub.ccp and V.sub.ini which are selectively supplied from the power supply scanning unit 50 through the power supply line 32, the first power supply voltage V.sub.ccp is a power supply voltage for supplying a drive current that drives the organic EL element 21 to emit light to the drive transistor 22. In addition, the second power supply voltage V.sub.ini is a power supply voltage for applying an inverse bias to the organic EL element 21. The second power supply voltage V.sub.ini is set to a voltage lower than the reference voltage V.sub.ofs, and for example, when the threshold voltage of the drive transistor 22 is set to V.sub.th, the second power supply voltage V.sub.ini is set to a voltage lower than V.sub.ofs-V.sub.th, and preferably to a voltage sufficiently lower than V.sub.ofs-V.sub.th.

[0059] Each pixel 20 of the pixel array unit 30 has the function of correcting variation of a drive current resulting from variation of characteristics of the drive transistor 22. Here, as the characteristics of the drive transistor 22, for example, the threshold voltage V.sub.th of the drive transistor 22, and a mobility u of a semiconductor thin film constituting a channel of the drive transistor 22 (which will be described hereinafter simply as “mobility u of the drive transistor 22”) are exemplified.

[0060] Correction of a variation of a drive current caused due to the variation of the threshold voltage V.sub.th (which will be described hereinafter as “threshold correction”) is performed by initializing a gate voltage V.sub.g of the drive transistor 22 to the reference voltage V.sub.ofs. To be specific, an operation of setting an initialization voltage (reference voltage V.sub.ofs) of the gate voltage V.sub.g of the drive transistor 22 as a reference and changing a source voltage V.sub.s of the drive transistor 22 toward a potential obtained by reducing the threshold voltage V.sub.th of the drive transistor 22 from the initialization voltage (reference voltage V.sub.ofs) is performed. When this operation progresses, a gate-source voltage V.sub.gs of the drive transistor 22 soon converges on the threshold voltage V.sub.th of the drive transistor 22. A voltage equivalent to the threshold voltage V.sub.th is retained in the retention capacitor 24. By retaining the voltage equivalent to the threshold voltage V.sub.th in the retention capacitor 24, it is possible to suppress dependency of a drain-source current I.sub.ds flowing through the drive transistor 22 on the threshold voltage V.sub.th when the drive transistor 22 is driven at the signal voltage V.sub.sig of a video signal.

[0061] Correction of a variation of a drive current caused due to a variation of the mobility u (which will be described hereinafter as “mobility correction”) is performed by flowing a current to the retention capacitor 24 via the drive transistor 22 in a state in which the writing transistor 23 enters a conductive state and the signal voltage V.sub.sig of the video signal is written. In other words, the correction is performed by applying negative feedback to the retention capacitor 24 with a feedback amount (correction amount) according to the current I.sub.ds flowing through the drive transistor 22. When a video signal is written through the correction of the threshold, the dependency of the drain-source current I.sub.ds on the threshold voltage V.sub.th disappears and the drain-source current I.sub.ds depends on the mobility u of the drive transistor 22. Accordingly, by applying negative feedback to the drain-source voltage Vas of the drive transistor 22 with the feedback amount according to the current I.sub.ds flowing through the drive transistor 22, it is possible to suppress the dependency of the drain-source current I.sub.ds flowing through the drive transistor 22 on the mobility u.

[Basic Circuit Configuration in Ideal State]

[0062] FIG. 3 is a timing waveform diagram for illustrating a basic circuit operation in an ideal state of the organic EL display device 10 having the above-described configuration. In the timing waveform diagram of FIG. 3, respective changes in the voltage (write scanning signals) WS of the scanning line 31, the voltage (power supply voltage) DS of the power supply line 32, the voltage (V.sub.sig/V.sub.ofs) of the signal line 33, and the gate voltage V.sub.g and the source voltage V.sub.s of the drive transistor 22 are shown.

[0063] Since the write transistor 23 is an N-channel type, the state of the high voltage of each write scanning signal WS is an active state, and the state of the low voltage thereof is a non-active state. Further, the write transistor 23 enters a conductive state in the active state of the write scanning signal WS, and enters a non-conductive state in the non-active state.

[0064] In the timing waveform diagram of FIG. 3, a period from time point t.sub.11 to time point t.sub.19 is a switching cycle of the voltages of the signal lines 33, that is, a switching cycle of the signal voltage V.sub.sig and the reference voltage V.sub.ofs of the video signal, and switching of the signal voltage V.sub.sig and the reference voltage V.sub.ofs is performed within 1 horizontal period (1H).

[0065] A time prior to time point t.sub.12 corresponds to a light emission period of the organic EL element 21 in a previous display frame. When the time reaches time point t.sub.12, a non-light-emission period of a new display frame (current display frame) in the line sequential scanning is started. Further, a period from time point t.sub.13 to time point t.sub.15 during which the write scanning signal WS enters the active state is a write period in which the write transistor 23 writes the reference voltage V.sub.ofs into the pixels 20. In addition, a period from time point t.sub.14 at which the voltage DS of each power supply line 32 is switched from the second power supply voltage V.sub.ini to the first power supply voltage V.sub.ccp to time point t.sub.15 at which the write scanning signal WS transitions to the non-active state is a threshold value correction period for correcting the variation of the drive current caused by the variation of the threshold value V.sub.th of the drive transistor 22.

[0066] Further, during a period from time point t.sub.16 to time point t.sub.19, the voltage of the signal line 33 becomes the signal voltage V.sub.sig of the video signal. In addition, during a period from time point t.sub.17 to time point t.sub.18, the write scanning signal WS enters the active state again, and the write transistor 23 enters the conductive state. Thus, the signal voltage V.sub.sig of the video signal is written into the pixel 20 by the write transistor 23, and a mobility correction process of correcting the variation of the drive current caused by the variation of the mobility u of the drive transistor 22 is performed. That is, the period from time point t.sub.17 to time point t.sub.18 is a write and mobility correction period of the signal voltage V.sub.sig. Then, when the time reaches time point t.sub.18, the light emission period of the current frame is started.

[0067] In the timing waveform diagram of FIG. 3, V.sub.cath is a cathode voltage of the organic EL element 21. Further, V.sub.thel is a threshold value voltage of the organic EL element 21.

[Shortening of Mobility Correction Time]

[0068] In the above-described organic EL display device 10, a change in the source voltage of the drive transistor 22 which is under a mobility correction operation is determined by a relationship between a current supply capability of the drive transistor 22 and a capacitance value of the pixel capacitor connected to the source electrode of the drive transistor 22. Specifically, a source voltage V of the drive transistor 22 after the mobility correction operation is given as the following Expression (1).

V = V sig – V th – 1 ( 1 V sig – V th – V s – .beta. 2 C t ) ( 1 ) ##EQU00001##

[0069] Here, V.sub.sig represents a signal voltage of a video signal, V.sub.th represents a threshold value voltage of the drive transistor 22, V.sub.s represents a source voltage of the drive transistor 22 before a mobility correction operation, t represents a mobility correction time, and .beta. represents a current supply capability of the drive transistor 22. Further, C represents a capacitance value of a pixel capacitor. In addition, when a capacitance value of the retention capacitor 24 is C.sub.s, a capacitance value of an equivalent capacitor of the organic EL element 21 is C.sub.oled, and a capacitance value of the auxiliary capacitor 25 is C.sub.sub, C=C.sub.s+C.sub.oled+C.sub.sub. Furthermore, the current supply capability .beta. of the drive transistor 22 is given as the expression .beta.=u.times.C.sub.ox.times.(W/L). Here, u represents a mobility of a semiconductor film that forms a channel of the drive transistor 22, C.sub.ox represents a gate capacitance per unit area of the drive transistor 22, W represents a channel width, and L represents a channel length.

[0070] It can be understood from Expression (1) that as the current supply capability .beta. of the drive transistor 22 increases and the capacitance value C of the pixel capacitor decreases, an increase (V.sub.s.fwdarw.V) of the source voltage of the drive transistor 22 at the same mobility correction time t becomes large.

[0071] That is, in a case in which the current supply capability .beta. of the drive transistor 22 is large and the capacitance value C of the pixel capacitor is small, as shown in FIG. 4A, an increasing speed of the source voltage V.sub.s of the drive transistor 22 which is under the mobility correction operation is fast, and thus the source voltage V.sub.s may reach a voltage value of V.sub.cath+V.sub.thel during writing of the signal voltage V.sub.sig. Further, since a current starts to flow in the organic EL element 21 at the moment at which the source voltage V.sub.S of the drive transistor 22 reaches the voltage value of V.sub.cath+V.sub.thel, mobility correction is not appropriately performed, or the organic EL element 21 erroneously emits light, which becomes a factor in deterioration of uniformity.

[0072] Thus, as shown in FIG. 4B, a driving method for shortening the mobility correction time (signal write and mobility correction period) and terminating the mobility correction operation before a current starts to flow in the organic EL element 21, that is, before the organic EL element 21 is turned on, is considered. The mobility correction time is determined by a pulse width of a mobility correction pulse which is a second pulse of the write scanning signal WS in the timing waveform diagram of FIG. 3. Accordingly, it is possible to shorten the mobility correction time by shortening the pulse width of the mobility correction pulse. Further, in accordance with this driving method, it is possible to suppress deterioration of uniformity due to turning-on of the organic EL element 21 during the mobility correction period.

[0073] However, in order to realize the driving for terminating the mobility correction operation before the above-mentioned driving, that is, before the organic EL element 21 is turned on, it is necessary to provide a circuit for generating a mobility correction pulse of a narrow (short) pulse width. Generally, a pulse signal of a pulse width of about several 100 nsec is input to the display panel 70, and generation of the write scanning signal WS including the mobility correction pulse is performed in the display panel 70 on the basis of the pulse signal. Under such an environment, in order to shorten the pulse width of the mobility correction pulse, specifically, in order to generate a mobility correction pulse of a pulse width of about several nsec, it is necessary to form a pulse width adjustment circuit on the display panel 70.

[Pulse Width Adjustment Circuit]

[0074] FIG. 5 shows a configuration example of a pulse width adjustment circuit in a peripheral circuit of the pixel array unit 30. FIG. 5 shows the pixel array unit 30, and the write scanning unit 40 which is one peripheral circuit thereof.

[0075] The write scanning unit 40 is configured by a shift register circuit, for example, and outputs shift signals WSSR.sub.1 to WSSR.sub.m from respective shift stages on the basis of a cross pulse WSCK and a start pulse WSST input from outside the display panel 70 through input terminals 71 and 72. The shift signals WSSR.sub.1 to WSSR.sub.m are supplied to respective pixel rows of the pixel array unit 30 as write scanning signals WS.sub.1 to SW.sub.m including mobility correction pulses through switch circuits 41.sub.1 to 41.sub.m provided for the each pixel row.

[0076] Further, enable signals WSEN.sub.1 and WSEN.sub.2 are input to a peripheral circuit on the display panel 70 through the input terminal 73 and 74. Pulse widths of the enable signals WSEN.sub.1 and WSEN.sub.2 are about several 100 nsec. The enable signals WSEN.sub.1 and WSEN.sub.2 are supplied to the pulse width adjustment circuit 80 through level shift (L/S) circuits 75 and 76. The pulse width adjustment circuit 80 is configured by a delay circuit unit 81 and a gate circuit unit 82.

[0077] The delay circuit unit 81 is a circuit part for determining a pulse width of a mobility correction pulse, and has a configuration in which a plurality of inverter circuits are connected in series. The gate circuit unit 82 is configured by a NAND circuit 821, an inverter circuit 822, a NOR circuit 823, and an inverter circuit 824. The NAND circuit 821 receives an input signal and an output signal of the delay circuit unit 81 as two inputs. An output signal of the NAND circuit 821 becomes one input signal A of the NOR circuit 823 through the inverter circuit 822. A pulse width of the input signal A is about several nsec, and becomes a pulse width of a mobility correction pulse.

[0078] The NOR circuit 823 receives the enable signal WSEN.sub.2 that has passed through the level shift circuit 76 as the other input signal. An output signal of the NOR circuit 823 is supplied to a buffer circuit 83 through the inverter circuit 824. The buffer circuit 83 has a configuration in which a plurality of inverter circuits are connected in series. An output signal B of the buffer circuit 83 is supplied to the switch circuits 41.sub.1 to 41.sub.m.

[0079] FIG. 6 shows waveforms of signals of the respective units in FIG. 5. Specifically, FIG. 6 shows respective waveforms of the cross pulse WSCK, the start pulse WSST, the enable signals WSEN.sub.1 and WSEN.sub.2, the one input signal A of the NOR circuit 823, and the output signal B of the buffer circuit 83. FIG. 6 further shows respective waveforms of the shift signals WSSR.sub.1, WSSR.sub.2, WSSR.sub.3, and WSSR.sub.4 corresponding to four pixel rows of the write scanning unit 40, and the write scanning signals WS.sub.1, WS.sub.2, WS.sub.3, and WS.sub.4 corresponding to four pixel rows.

更多阅读推荐......