Samsung Patent | Sub-pixel, display device including the sub-pixel, and display system including the display device

Patent: Sub-pixel, display device including the sub-pixel, and display system including the display device

Publication Number: 20250308448

Publication Date: 2025-10-02

Assignee: Samsung Display

Abstract

A sub-pixel includes a first transistor connected between a first node and a second node and including a gate electrode connected to a third node, a second transistor connected between a data line and the third node and including a gate electrode connected to a first sub-gate line, a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and including a gate electrode connected to an emission control line, and a light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage. Body electrodes of the first transistor through the third transistor are biased with at least one voltage. The sub-pixel further includes a capacitor connected between the first node and the third node.

Claims

What is claimed is:

1. A sub-pixel included in a display device comprising:a first transistor connected between a first node and a second node and comprising a gate electrode connected to a third node;a second transistor connected between a data line and the third node and comprising a gate electrode connected to a first sub-gate line;a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and comprising a gate electrode connected to an emission control line; anda light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage,wherein body electrodes of the first transistor through the third transistor are biased with at least one voltage, andwherein the sub-pixel further comprises a capacitor connected between the first node and the third node, without a capacitor connected to the second node and the third node.

2. The sub-pixel of claim 1, wherein the first power source voltage is applied to the body electrode of the first transistor.

3. The sub-pixel of claim 1, wherein the sub-pixel does not comprise any capacitors other than the capacitor.

4. The sub-pixel of claim 1, further comprising:a fourth transistor connected between the second node and an initialization voltage node configured to supply an initialization voltage and comprising a gate electrode connected to a second sub-gate line.

5. The sub-pixel of claim 4, wherein the first power source voltage is commonly applied to the body electrodes of the first transistor through the third transistor and a body electrode of the fourth transistor.

6. The sub-pixel of claim 4, wherein each of the first transistor through the fourth transistor is a PMOS (P-channel Metal Oxide Semiconductor) transistor.

7. The sub-pixel of claim 4, wherein the first transistor through the fourth transistor are mounted on a silicon substrate.

8. A display device comprising:sub-pixels connected to gate lines and emission control lines; anda gate driver configured to control the gate lines and the emission control lines,wherein a sub-pixel of the sub-pixels comprises:a first transistor connected between a first node and a second node and comprising a gate electrode connected to a third node;a second transistor connected between a data line and the third node and comprising a gate electrode connected to a first sub-gate line of one of the gate lines;a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and comprising a gate electrode connected to one of the emission control lines; anda light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage,wherein body electrodes of the first transistor through the third transistor are biased with at least one voltage, andwherein the sub-pixel further comprises a capacitor connected between the first node and the third node, without a capacitor connected to the second node and the third node.

9. The display device of claim 8, wherein the first power source voltage is applied to the body electrode of the first transistor.

10. The display device of claim 8, wherein the sub-pixel does not comprise any capacitors other than the capacitor.

11. The display device of claim 8, wherein the sub-pixel further comprises a fourth transistor connected between the second node and an initialization voltage node configured to supply an initialization voltage and comprising a gate electrode connected to a second sub-gate line of the one of the gate lines.

12. The display device of claim 11, wherein the first power source voltage is commonly applied to the body electrodes of the first transistor through the third transistor and a body electrode of the fourth transistor.

13. The display device of claim 11, wherein the gate driver is configured to:turn on the fourth transistor by supplying a second scan signal set to logic low level to the second sub-gate line during a first period, a second period, and a third period provided sequentially,turn on the second transistor by supplying a first scan signal set to logic low level to the first sub-gate line and to turn off the third transistor by supplying an emission control signal set to logic high level to the one of the emission control lines, during the second period,turn off the second transistor by setting the first scan signal to logic high level during the third period, andturn off the fourth transistor by setting the second scan signal to logic high level and turn on the third transistor by setting the emission control signal to logic low level, during a fourth period.

14. The display device of claim 13, further comprising:a data driver configured to control the data line,wherein the data driver is configured to supply a data signal to the data line during the second period.

15. The display device of claim 14, wherein during the second period, the data signal of the data line is reflected in a voltage of the third node through the second transistor, andwherein during the fourth period, current is supplied from the first power source voltage node to the light emitting element through the third transistor and the first transistor according to the voltage of the third node.

16. A display system comprising:a processor; andat least one display device to display images on sub-pixels based on image data from the processor,wherein one of the sub-pixels comprises:a first transistor connected between a first node and a second node and comprising a gate electrode connected to a third node;a second transistor connected between a data line and the third node and comprising a gate electrode connected to a first sub-gate line;a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and comprising a gate electrode connected to an emission control line; anda light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage,wherein body electrodes of the first transistor through the third transistor are biased with at least one voltage, andwherein the one of the sub-pixels further comprises a capacitor connected between the first node and the third node, without a capacitor connected to the second node and the third node.

Description

This application claims priority to Korean Patent Application No. 10-2024-0043179, filed on Mar. 29, 2024, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.

BACKGROUND

Field

Embodiments supported by the present disclosure relates to an electronic device, and more specifically, to a sub-pixel, a display device including the sub-pixel, and a display system including the display device.

Description of the Related Art

As information technology develops, the importance of a display device as a connection medium between a user and information is being emphasized. In response to this, the use of display devices such as, for example, a liquid crystal display device and an organic light emitting display device is increasing.

Recently, a head-mounted display device (HMD) has been developed. The head-mounted display device is a display device worn by a user in the form of glasses or a helmet and implements virtual reality (VR) or augmented reality (AR) that is focused close to the eyes. A high-resolution panel is applied to the head-mounted display device, and accordingly, sub-pixels applicable to the high-resolution panel may be required.

The above description is for helping the understanding of the background art for the technical ideas of the present invention. Therefore, it should not be understood as the contents corresponding to the prior art known to those skilled in the art to which the present invention pertains.

SUMMARY

Embodiments of the present invention provide a display device including high-resolution sub-pixels.

Embodiments of the present invention provide a display device including sub-pixels that can be manufactured at reduced cost.

A sub-pixel included in a display device according to an embodiment supported by the present disclosure may include a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the third node and including a gate electrode connected to a first sub-gate line; a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and including a gate electrode connected to an emission control line; and a light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage. Body electrodes of the first transistor through the third transistor are biased with at least one voltage. The sub-pixel further includes a capacitor connected between the first node and the third node, without a capacitor connected to the second node and the third node.

The first power source voltage may be applied to the body electrode of the first transistor.

The sub-pixel may not include any capacitors other than the capacitor.

The sub-pixel may further include a fourth transistor connected between the second node and an initialization voltage node configured to supply an initialization voltage and including a gate electrode connected to a second sub-gate line.

The first power source voltage may be commonly applied to the body electrodes of the first transistor through the third transistor and a body electrode of the fourth transistor.

Each of the first transistor through the fourth transistor may be a PMOS (P-channel Metal Oxide Semiconductor) transistor.

The first transistor through the fourth transistor may be mounted on a silicon substrate.

The initialization voltage may be equal to or lower than the second power source voltage.

Another aspect of the present invention relates to a display device. A display device according to an embodiment supported by the present disclosure may include sub-pixels connected to gate lines and emission control lines; and a gate driver configured to control the gate lines and the emission control lines. A sub-pixel of the sub-pixels may include a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the third node and including a gate electrode connected to a first sub-gate line of one of the gate lines; a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and including a gate electrode connected to one of the emission control lines; and a light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage. Body electrodes of the first transistor through the third transistor are biased with at least one voltage. The sub-pixel further includes a capacitor connected between the first node and the third node, without a capacitor connected to the second node and the third node.

The first power source voltage may be applied to the body electrode of the first transistor.

The sub-pixel may not include any capacitors other than the capacitor.

The sub-pixel may further include a fourth transistor connected between the second node and an initialization voltage node configured to supply an initialization voltage and including a gate electrode connected to a second sub-gate line of the one of the gate lines.

The first power source voltage may be commonly applied to the body electrodes of the first transistor through the third transistor and a body electrode of the fourth transistor.

The gate driver may be configured to: turn on the fourth transistor by supplying a second scan signal set to logic low level to the second sub-gate line during a first period, a second period, and a third period provided sequentially, turn on the second transistor by supplying a first scan signal set to logic low level to the first sub-gate line and to turn off the third transistor by supplying an emission control signal set to logic high level to the one of the emission control lines, during the second period, turn off the second transistor by setting the first scan signal to logic high level during the third period, and turn off the fourth transistor by setting the second scan signal to logic high level and turn on the third transistor by setting the emission control signal to logic low level, during a fourth period.

The display device may further include a data driver configured to control the data line. The data driver may be configured to supply a data signal to the data line during the second period.

During the second period, the data signal of the data line may be reflected in a voltage of the third node through the second transistor. During the fourth period, current may be supplied from the first power source voltage node to the light emitting element through the third transistor and the first transistor according to the voltage of the third node.

Still another aspect of the present invention relates to a display system. The display system according to an embodiment supported by the present disclosure may include a processor; and at least one display device to display images on sub-pixels based on image data from the processor. One of the sub-pixels includes: a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the third node and including a gate electrode connected to a first sub-gate line; a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and including a gate electrode connected to an emission control line; and a light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage. Body electrodes of the first transistor through the third transistor are biased with at least one voltage. The one of the sub-pixels further includes a capacitor connected between the first node and the third node, without a capacitor connected to the second node and the third node.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the inventive concepts, and are incorporated in and constitute a part of this specification, illustrate example embodiments of the inventive concepts, and, together with the description, serve to explain principles of the inventive concepts.

FIG. 1 is a block diagram of a display device according to an embodiment supported by the present disclosure.

FIG. 2 is a block diagram illustrating an embodiment of a sub-pixel of FIG. 1.

FIG. 3 is a block diagram illustrating an embodiment of a display panel and a gate driver of FIG. 1.

FIG. 4 is a circuit diagram illustrating an embodiment of the sub-pixel of FIG. 2.

FIG. 5 is a timing diagram illustrating an embodiment of signals provided to the sub-pixel of FIG. 4 during a display operation.

FIGS. 6 to 9 are diagrams for explaining operations of the sub-pixel in first to fourth periods of FIG. 5.

FIG. 10 is a plan view illustrating an embodiment of the display panel of FIG. 1.

FIG. 11 is an exploded perspective view illustrating a portion of the display panel of FIG. 10.

FIG. 12 is a block diagram illustrating an embodiment of a display system.

FIG. 13 is a perspective view illustrating an application example of the display system of FIG. 12.

FIG. 14 is a diagram illustrating a head-mounted display device worn by a user.