Meta Patent | Aln-based hybrid bonding

where η_EQE is the external quantum efficiency of image source 412, η_in is the in-coupling efficiency of light from image source 412 into the waveguide (e.g., substrate 420), and η_out is the outcoupling efficiency of light from the waveguide towards the user's eye by output coupler 440. Thus, the overall efficiency η_tot of the waveguide-based display can be improved by improving one or more of η_EQE, η_in, and η_out.

The optical coupler (e.g., input coupler 430 or coupler 532) that couples the emitted light from a light source to a waveguide may include, for example, a grating, a lens, a micro-lens, and/or a prism. In some embodiments, light from a small light source (e.g., a micro-LED) can be directly (e.g., end-to-end) coupled from the light source to a waveguide, without using an optical coupler. In some embodiments, the optical coupler (e.g., a lens or a parabolic-shaped reflector) may be manufactured on the light source.

The light sources, image sources, or other displays described above may include one or more LEDs. For example, each pixel in a display may include three subpixels that include a red micro-LED, a green micro-LED, and a blue micro-LED. A semiconductor light emitting diode generally includes an active light emitting layer within multiple layers of semiconductor materials. The multiple layers of semiconductor materials may include different compound materials or a same base material with different dopants and/or different doping densities. For example, the multiple layers of semiconductor materials may generally include an n-type material layer, an active layer that may include hetero-structures (e.g., one or more quantum wells), and a p-type material layer. The multiple layers of semiconductor materials may be grown on a surface of a substrate having a certain orientation.

Photons can be generated in a semiconductor LED (e.g., a micro-LED) at a certain internal quantum efficiency through the recombination of electrons and holes within the active layer (e.g., including one or more semiconductor layers). The generated light may then be extracted from the LEDs. The ratio between the number of emitted photons extracted from the LED and the number of electrons passing through the LED is referred to as the external quantum efficiency, which describes how efficiently the LED converts injected electrons to photons that are extracted from the device. The external quantum efficiency may be proportional to the carrier injection efficiency, the internal quantum efficiency, and the light extraction efficiency. The carrier injection efficiency refers to the proportion of electrons passing through the device that are injected into the active region. The light extraction efficiency is the proportion of photons generated in the active region that escape from the device. For LEDs, and in particular, micro-LEDs with reduced physical dimensions, improving the internal and external quantum efficiency can be challenging. In some embodiments, to increase the light extraction efficiency of an LED, a mesa structure may be etched in semiconductor epitaxial layers, and light extraction structures (e.g., reflectors, lenses, and/or rough surfaces) may be formed on the mesa structure.

FIG. 7A illustrates an example of an LED 700 having a vertical mesa structure. LED 700 may be a light emitter in light source 510, 540, or 642. LED 700 may be a micro-LED made of inorganic materials, such as multiple layers of semiconductor materials. The layered semiconductor light emitting device may include multiple layers of III-V semiconductor materials. A III-V semiconductor material may include one or more Group III elements, such as aluminum (Al), gallium (Ga), or indium (In), in combination with a Group V element, such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). When the Group V element of the III-V semiconductor material includes nitrogen, the III-V semiconductor material is referred to as a III-nitride material. The layered semiconductor light emitting device may be manufactured by growing multiple epitaxial layers on a substrate using techniques such as vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular beam epitaxy (MBE), or metalorganic chemical vapor deposition (MOCVD). For example, the layers of the semiconductor materials may be grown layer-by-layer on a substrate with a certain crystal lattice orientation (e.g., polar, nonpolar, or semi-polar orientation), such as a GaN, GaAs, or GaP substrate, or a substrate including, but not limited to, sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinels, or quaternary tetragonal oxides sharing the beta-LiAlO₂ structure, where the substrate may be cut in a specific direction to expose a specific plane as the growth surface.

In the example shown in FIG. 7A, LED 700 may include a substrate 710, which may include, for example, a sapphire substrate or a GaN substrate. A semiconductor layer 720 may be grown on substrate 710. Semiconductor layer 720 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One or more active layers 730 may be grown on semiconductor layer 720 to form an active region. Active layer 730 may include III-V materials, such as one or more InGaN layers, one or more AlGaInP layers, and/or one or more GaN layers, which may form one or more heterostructures, such as one or more quantum wells or MQWs. A semiconductor layer 740 may be grown on active layer 730. Semiconductor layer 740 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One of semiconductor layer 720 and semiconductor layer 740 may be a p-type layer and the other one may be an n-type layer. Semiconductor layer 720 and semiconductor layer 740 sandwich active layer 730 to form the light emitting region. For example, LED 700 may include a layer of InGaN situated between a layer of p-type GaN doped with magnesium and a layer of n-type GaN doped with silicon or oxygen. In some embodiments, LED 700 may include a layer of AlGaInP situated between a layer of p-type AlGaInP doped with zinc or magnesium and a layer of n-type AlGaInP doped with selenium, silicon, or tellurium.

In some embodiments, an electron-blocking layer (EBL) (not shown in FIG. 7A) may be grown to form a layer between active layer 730 and at least one of semiconductor layer 720 or semiconductor layer 740. The EBL may reduce the electron leakage current and improve the efficiency of the LED. In some embodiments, a heavily-doped semiconductor layer 750, such as a P⁺ or P⁺⁺ semiconductor layer, may be formed on semiconductor layer 740 and act as a contact layer for forming an ohmic contact and reducing the contact impedance of the device. In some embodiments, a conductive layer 760 may be formed on heavily-doped semiconductor layer 750. Conductive layer 760 may include, for example, an indium tin oxide (ITO) or Al/Ni/Au film. In one example, conductive layer 760 may include a transparent ITO layer.

To make contact with semiconductor layer 720 (e.g., an n-GaN layer) and to more efficiently extract light emitted by active layer 730 from LED 700, the semiconductor material layers (including heavily-doped semiconductor layer 750, semiconductor layer 740, active layer 730, and semiconductor layer 720) may be etched to expose semiconductor layer 720 and to form a mesa structure that includes layers 720-760. The mesa structure may confine the carriers within the device. Etching the mesa structure may lead to the formation of mesa sidewalls 732 that may be orthogonal to the growth planes. A passivation layer 770 may be formed on mesa sidewalls 732 of the mesa structure. Passivation layer 770 may include an oxide layer, such as a SiO₂ layer, and may act as a reflector to reflect emitted light out of LED 700. A contact layer 780, which may include a metal layer, such as Al, Au, Ni, Ti, or any combination thereof, may be formed on semiconductor layer 720 and may act as an electrode of LED 700. In addition, another contact layer 790, such as an Al/Ni/Au metal layer, may be formed on conductive layer 760 and may act as another electrode of LED 700.

When a voltage signal is applied to contact layers 780 and 790, electrons and holes may recombine in active layer 730, where the recombination of electrons and holes may cause photon emission. The wavelength and energy of the emitted photons may depend on the energy bandgap between the valence band and the conduction band in active layer 730. For example, InGaN active layers may emit green or blue light, AlGaN active layers may emit blue to ultraviolet light, while AlGaInP active layers may emit red, orange, yellow, or green light. The emitted photons may be reflected by passivation layer 770 and may exit LED 700 from the top (e.g., conductive layer 760 and contact layer 790) or bottom (e.g., substrate 710).

In some embodiments, LED 700 may include one or more other components, such as a lens, on the light emission surface, such as substrate 710, to focus or collimate the emitted light or couple the emitted light into a waveguide. In some embodiments, an LED may include a mesa of another shape, such as planar, conical, semi-parabolic, or parabolic, and a base area of the mesa may be circular, rectangular, hexagonal, or triangular. For example, the LED may include a mesa of a curved shape (e.g., paraboloid shape) and/or a non-curved shape (e.g., conic shape). The mesa may be truncated or non-truncated.

FIG. 7B is a cross-sectional view of an example of an LED 705 having a parabolic mesa structure. Similar to LED 700, LED 705 may include multiple layers of semiconductor materials, such as multiple layers of III-V semiconductor materials. The semiconductor material layers may be epitaxially grown on a substrate 715, such as a GaN substrate or a sapphire substrate. For example, a semiconductor layer 725 may be grown on substrate 715. Semiconductor layer 725 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One or more active layer 735 may be grown on semiconductor layer 725. Active layer 735 may include III-V materials, such as one or more InGaN layers, one or more AlGaInP layers, and/or one or more GaN layers, which may form one or more heterostructures, such as one or more quantum wells. A semiconductor layer 745 may be grown on active layer 735. Semiconductor layer 745 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One of semiconductor layer 725 and semiconductor layer 745 may be a p-type layer and the other one may be an n-type layer.

To make contact with semiconductor layer 725 (e.g., an n-type GaN layer) and to more efficiently extract light emitted by active layer 735 from LED 705, the semiconductor layers may be etched to expose semiconductor layer 725 and to form a mesa structure that includes layers 725-745. The mesa structure may confine carriers within the injection area of the device. Etching the mesa structure may lead to the formation of mesa side walls (also referred to herein as facets) that may be non-parallel with, or in some cases, orthogonal, to the growth planes associated with crystalline growth of layers 725-745.

As shown in FIG. 7B, LED 705 may have a mesa structure that includes a flat top. A dielectric layer 775 (e.g., SiO₂ or SiN) may be formed on the facets of the mesa structure. In some embodiments, dielectric layer 775 may include multiple layers of dielectric materials. In some embodiments, a metal layer 795 may be formed on dielectric layer 775. Metal layer 795 may include one or more metal or metal alloy materials, such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), copper (Cu), or any combination thereof. Dielectric layer 775 and metal layer 795 may form a mesa reflector that can reflect light emitted by active layer 735 toward substrate 715. In some embodiments, the mesa reflector may be parabolic-shaped to act as a parabolic reflector that may at least partially collimate the emitted light.

Electrical contact 765 and electrical contact 785 may be formed on semiconductor layer 745 and semiconductor layer 725, respectively, to act as electrodes. Electrical contact 765 and electrical contact 785 may each include a conductive material, such as Al, Au, Pt, Ag, Ni, Ti, Cu, or any combination thereof (e.g., Ag/Pt/Au or Al/Ni/Au), and may act as the electrodes of LED 705. In the example shown in FIG. 7B, electrical contact 785 may be an n-contact, and electrical contact 765 may be a p-contact. Electrical contact 765 and semiconductor layer 745 (e.g., a p-type semiconductor layer) may form a back reflector for reflecting light emitted by active layer 735 back toward substrate 715. In some embodiments, electrical contact 765 and metal layer 795 include same material(s) and can be formed using the same processes. In some embodiments, an additional conductive layer (not shown) may be included as an intermediate conductive layer between the electrical contacts 765 and 785 and the semiconductor layers.

When a voltage signal is applied across electrical contacts 765 and 785, electrons and holes may recombine in active layer 735. The recombination of electrons and holes may cause photon emission, thus producing light. The wavelength and energy of the emitted photons may depend on the energy bandgap between the valence band and the conduction band in active layer 735. For example, InGaN active layers may emit green or blue light, while AlGaInP active layers may emit red, orange, yellow, or green light. The emitted photons may propagate in many different directions, and may be reflected by the mesa reflector and/or the back reflector and may exit LED 705, for example, from the bottom side (e.g., substrate 715) shown in FIG. 7B. One or more other secondary optical components, such as a lens or a grating, may be formed on the light emission surface, such as substrate 715, to focus or collimate the emitted light and/or couple the emitted light into a waveguide.

When the mesa structure is formed (e.g., etched), the facets of the mesa structure, such as mesa sidewalls 732, may have high defect densities due to the abrupt ending of the lattice structure, chemical contamination, and/or structural damages (e.g., due to dry etch). For example, in plasma etching, high-energy ions may be used to bombard the exposed surfaces of semiconductor layers. Due to the bombardment by high-energy particles, the surfaces created by the etching may be highly damaged, where the damages may include alterations to the crystal structure or other modifications to the surfaces, such as dangling-bonds, surface oxides, surfaces modified by plasma atoms, lattice dislocations, vacancies, interstitial defects, and substitutional defects. The damages may extend into the interior of the mesa structure, such as about 50 nm to about 500 nm below the new surfaces formed by the etching. Therefore, the active region in proximity to the exposed sidewalls may have a higher density of defects, such as dislocations, dangling bonds, pores, grain boundaries, vacancies, inclusion of precipitates, and the like. The defects may introduce energy states having deep or shallow energy levels in the bandgap that otherwise would not exist within the bandgap of the semiconductor material. Carriers may be trapped by these energy states until they recombine non-radiatively. Thus, these imperfections may become the recombination centers where electrons and holes may be confined until they combine non-radiatively.Therefore, the active region in proximity to the exposed sidewalls may have a higher rate of SRH recombination, thereby reducing the efficiency of the resulting LED.

FIG. 8A illustrates an example of a method of die-to-wafer bonding for arrays of LEDs according to certain embodiments. In the example shown in FIG. 8A, an LED array 801 may include a plurality of LEDs 807 on a carrier substrate 805. Carrier substrate 805 may include various materials, such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. LEDs 807 may be fabricated by, for example, growing various epitaxial layers, forming mesa structures, and forming electrical contacts or electrodes, before performing the bonding. The epitaxial layers may include various materials, such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP, (AlGaIn)AsN, (Eu:InGa)N, (AlGaIn)N, or the like, and may include an n-type layer, a p-type layer, and an active layer that includes one or more heterostructures, such as one or more quantum wells or MQWs. The electrical contacts may include various conductive materials, such as a metal, a metal alloy, a conductive nitride (e.g., a nitride of a transitional metal), or a transparent conductive coating (e.g., an oxide such as ITO).

A wafer 803 may include a base layer 809 having passive or active integrated circuits (e.g., drive circuits 811) fabricated thereon. Base layer 809 may include, for example, a silicon wafer. Drive circuits 811 may be used to control the operations of LEDs 807. For example, the drive circuit for each LED 807 may include a 2T1C pixel structure that has two transistors and one capacitor. Wafer 803 may also include a bonding layer 813. Bonding layer 813 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, and the like. In some embodiments, a patterned layer 815 may be formed on a surface of bonding layer 813, where patterned layer 815 may include a metallic grid made of a conductive material, such as Cu, Ag, Au, Al, or the like.

LED array 801 may be bonded to wafer 803 via bonding layer 813 or patterned layer 815. For example, patterned layer 815 may include metal pads or bumps made of various materials, such as CuSn, AuSn, or nanoporous Au, that may be used to align LEDs 807 of LED array 801 with corresponding drive circuits 811 on wafer 803. In one example, LED array 801 may be brought toward wafer 803 until LEDs 807 come into contact with respective metal pads or bumps corresponding to drive circuits 811. Some or all of LEDs 807 may be aligned with drive circuits 811, and may then be bonded to wafer 803 via patterned layer 815 by various bonding techniques, such as metal-to-metal bonding. After LEDs 807 have been bonded to wafer 803, carrier substrate 805 may be removed from LEDs 807.

FIG. 8B illustrates an example of a method of wafer-to-wafer bonding for arrays of LEDs according to certain embodiments. As shown in FIG. 8B, a first wafer 802 may include a substrate 804, a first semiconductor layer 806, active layers 808, and a second semiconductor layer 810. Substrate 804 may include various materials, such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. First semiconductor layer 806, active layers 808, and second semiconductor layer 810 may include various semiconductor materials, such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP, (AlGaIn)AsN, (Eu:InGa)N, (AlGaIn)N, or the like. In some embodiments, first semiconductor layer 806 may be an n-type layer, and second semiconductor layer 810 may be a p-type layer. For example, first semiconductor layer 806 may be an n-doped GaN layer (e.g., doped with Si or Ge), and second semiconductor layer 810 may be a p-doped GaN layer (e.g., doped with Mg, Ca, Zn, or Be). Active layers 808 may include, for example, one or more GaN layers, one or more InGaN layers, one or more AlInGaP layers, and the like, which may form one or more heterostructures, such as one or more quantum wells or MQWs.

In some embodiments, first wafer 802 may also include a bonding layer. Bonding layer 812 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, or the like. In one example, bonding layer 812 may include p-contacts and/or n-contacts (not shown). In some embodiments, other layers may also be included on first wafer 802, such as a buffer layer between substrate 804 and first semiconductor layer 806. The buffer layer may include various materials, such as polycrystalline GaN or AlN. In some embodiments, a contact layer may be between second semiconductor layer 810 and bonding layer 812. The contact layer may include any suitable material for providing an electrical contact to second semiconductor layer 810 and/or first semiconductor layer 806.

First wafer 802 may be bonded to wafer 803 that includes drive circuits 811 and bonding layer 813 as described above, via bonding layer 813 and/or bonding layer 812. Bonding layer 812 and bonding layer 813 may be made of the same material or different materials. Bonding layer 813 and bonding layer 812 may be substantially flat. First wafer 802 may be bonded to wafer 803 by various methods, such as metal-to-metal bonding, eutectic bonding, metal oxide bonding, anodic bonding, thermo-compression bonding, ultraviolet (UV) bonding, and/or fusion bonding.

As shown in FIG. 8B, first wafer 802 may be bonded to wafer 803 with the p-side (e.g., second semiconductor layer 810) of first wafer 802 facing down (i.e., toward wafer 803). After bonding, substrate 804 may be removed from first wafer 802, and first wafer 802 may then be processed from the n-side. The processing may include, for example, the formation of certain mesa shapes for individual LEDs, as well as the formation of optical components corresponding to the individual LEDs.

FIGS. 9A-9D illustrate an example of a method of hybrid bonding for arrays of LEDs according to certain embodiments. The hybrid bonding may generally include wafer cleaning and activation, high-precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials at the surfaces of the wafers at room temperature, and metal bonding of the contacts by annealing at elevated temperatures. FIG. 9A shows a substrate 910 with passive or active circuits 920 manufactured thereon. As described above with respect to FIGS. 8A-8B, substrate 910 may include, for example, a silicon wafer. Circuits 920 may include drive circuits for the arrays of LEDs. A bonding layer may include dielectric regions 940 and contact pads 930 connected to circuits 920 through electrical interconnects 922. Contact pads 930 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like. Dielectric materials in dielectric regions 940 may include SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, where the planarization or polishing may cause dishing (a bowl like profile) in the contact pads. The surfaces of the bonding layers may be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., Ar) beam 905. The activated surface may be atomically clean and may be reactive for formation of direct bonds between wafers when they are brought into contact, for example, at room temperature.

FIG. 9B illustrates a wafer 950 including an array of micro-LEDs 970 fabricated thereon as described above. Wafer 950 may be a carrier wafer and may include, for example, GaAs, InP, GaN, AN, sapphire, SiC, Si, or the like. Micro-LEDs 970 may include an n-type layer, an active region, and a p-type layer epitaxially grown on wafer 950. The epitaxial layers may include various III-V semiconductor materials described above, and may be processed from the p-type layer side to etch mesa structures in the epitaxial layers, such as substantially vertical structures, parabolic structures, conic structures, or the like. Passivation layers and/or reflection layers may be formed on the sidewalls of the mesa structures. P-contacts 980 and n-contacts 982 may be formed in a dielectric material layer 960 deposited on the mesa structures and may make electrical contacts with the p-type layer and the n-type layers, respectively. Dielectric materials in dielectric material layer 960 may include, for example, SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like. P-contacts 980 and n-contacts 982 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like. The top surfaces of p-contacts 980, n-contacts 982, and dielectric material layer 960 may form a bonding layer. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, where the polishing may cause dishing in p-contacts 980 and n-contacts 982. The bonding layer may then be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., Ar) beam 915. The activated surface may be atomically clean and reactive for formation of direct bonds between wafers when they are brought into contact, for example, at room temperature.

FIG. 9C illustrates a room temperature bonding process for bonding the dielectric materials in the bonding layers. For example, after the bonding layer that includes dielectric regions 940 and contact pads 930 and the bonding layer that includes p-contacts 980, n-contacts 982, and dielectric material layer 960 are surface activated, wafer 950 and micro-LEDs 970 may be turned upside down and brought into contact with substrate 910 and the circuits formed thereon. In some embodiments, compression pressure 925 may be applied to substrate 910 and wafer 950 such that the bonding layers are pressed against each other. Due to the surface activation and the dishing in the contacts, dielectric regions 940 and dielectric material layer 960 may be in direct contact because of the surface attractive force, and may react and form chemical bonds between them because the surface atoms may have dangling bonds and may be in unstable energy states after the activation. Thus, the dielectric materials in dielectric regions 940 and dielectric material layer 960 may be bonded together with or without heat treatment or pressure.

FIG. 9D illustrates an annealing process for bonding the contacts in the bonding layers after bonding the dielectric materials in the bonding layers. For example, contact pads 930 and p-contacts 980 or n-contacts 982 may be bonded together by annealing at, for example, about 90-400° C. or higher. During the annealing process, heat 935 may cause the contacts to expand more than the dielectric materials (due to different coefficients of thermal expansion), and thus may close the dishing gaps between the contacts such that contact pads 930 and p-contacts 980 or n-contacts 982 may be in contact and may form direct metallic bonds at the activated surfaces.

In some embodiments where the two bonded wafers include materials having different coefficients of thermal expansion (CTEs), the dielectric materials bonded at room temperature may help to reduce or prevent misalignment of the contact pads caused by the different thermal expansions. In some embodiments, to further reduce or avoid the misalignment of the contact pads at a high temperature during annealing, trenches may be formed between micro-LEDs, between groups of micro-LEDs, through part or all of the substrate, or the like, before bonding.

After the micro-LEDs are bonded to the drive circuits, the substrate on which the micro-LEDs are fabricated may be thinned or removed, and various secondary optical components may be fabricated on the light emitting surfaces of the micro-LEDs to, for example, extract, collimate, and redirect the light emitted from the active regions of the micro-LEDs. In one example, micro-lenses may be formed on the micro-LEDs, where each micro-lens may correspond to a respective micro-LED and may help to improve the light extraction efficiency and collimate the light emitted by the micro-LED. In some embodiments, the secondary optical components may be fabricated in the substrate or the n-type layer of the micro-LEDs. In some embodiments, the secondary optical components may be fabricated in a dielectric layer deposited on the n-type side of the micro-LEDs. Examples of the secondary optical components may include a lens, a grating, an antireflection (AR) coating, a prism, a photonic crystal, or the like.

FIG. 10 illustrates an example of an LED array 1000 with secondary optical components fabricated thereon according to certain embodiments. LED array 1000 may be made by bonding an LED chip or wafer with a silicon wafer including electrical circuits fabricated thereon, using any suitable bonding techniques described above with respect to, for example, FIGS. 8A-9D. In the example shown in FIG. 10, LED array 1000 may be bonded using a wafer-to-wafer hybrid bonding technique as described above with respect to FIG. 9A-9D. LED array 1000 may include a substrate 1010, which may be, for example, a silicon wafer. Integrated circuits 1020, such as LED drive circuits, may be fabricated on substrate 1010. Integrated circuits 1020 may be connected to p-contacts 1074 and n-contacts 1072 of micro-LEDs 1070 through interconnects 1022 and contact pads 1030, where contact pads 1030 may form metallic bonds with p-contacts 1074 and n-contacts 1072. Dielectric layer 1040 on substrate 1010 may be bonded to dielectric layer 1060 through fusion bonding.

The substrate (not shown) of the LED chip or wafer may be thinned or may be removed to expose the n-type layer 1050 of micro-LEDs 1070. Various secondary optical components, such as a spherical micro-lens 1082, a grating 1084, a micro-lens 1086, an antireflection layer 1088, and the like, may be formed in or on top of n-type layer 1050. For example, spherical micro-lens arrays may be etched in the semiconductor materials of micro-LEDs 1070 using a gray-scale mask and a photoresist with a linear response to exposure light, or using an etch mask formed by thermal reflowing of a patterned photoresist layer. The secondary optical components may also be etched in a dielectric layer deposited on n-type layer 1050 using similar photolithographic techniques or other techniques. For example, micro-lens arrays may be formed in a polymer layer through thermal reflowing of the polymer layer that is patterned using a binary mask. The micro-lens arrays in the polymer layer may be used as the secondary optical components or may be used as the etch mask for transferring the profiles of the micro-lens arrays into a dielectric layer or a semiconductor layer. The dielectric layer may include, for example, SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like. In some embodiments, a micro-LED 1070 may have multiple corresponding secondary optical components, such as a micro-lens and an anti-reflection coating, a micro-lens etched in the semiconductor material and a micro-lens etched in a dielectric material layer, a micro-lens and a grating, a spherical lens and an aspherical lens, and the like. Three different secondary optical components are illustrated in FIGS. 10 to show some examples of secondary optical components that can be formed on micro-LEDs 1070, which does not necessary imply that different secondary optical components are used simultaneously for every LED array.

FIGS. 11A-11E illustrate an example of a method of fabricating a micro-LED device according to certain embodiments. FIG. 11A shows a micro-LED wafer 1100 including epitaxial layers grown on a substrate 1110. As described above, substrate 1110 may include, for example, a GaN, GaAs, or GaP substrate, or a substrate including, but not limited to, sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinels, or quaternary tetragonal oxides sharing the beta-LiAlP₂ structure, where the substrate may be cut in a specific direction to expose a specific plane (e.g., a c-plane, an m-plane, or a semipolar plane) as the growth surface.

In some embodiments, a buffer layer (e.g., an AlN layer) may be formed on substrate 1110 to improve the lattice matching between the growth substrate and the epitaxial layers, thereby reducing stress and defects in the epitaxial layers. The epitaxial layers may include an n-type semiconductor layer 1120 (e.g., an n-doped GaN, AlInP, or AlGaInP layer), an active region 1130, and a p-type semiconductor layer 1140 (e.g., a p-doped GaN, AlInP, or AlGaInP layer). Active region 1130 may include multiple quantum wells or an MQW formed by thin quantum well layers (e.g., InGaN layers or GaInP layers) sandwiched by barrier layers (e.g., GaN layers, AlInP layers, or AlGaInP layers) as described above. The epitaxial layers may be grown layer-by-layer on substrate 1110 or the buffer layer using techniques such as VPE, LPE, MBE, or MOCVD. In some embodiments, n-type semiconductor layer 1120 may be thicker than p-type semiconductor layer 1140.

FIG. 11B shows that micro-LED wafer 1100 may be etched from the side of p-type semiconductor layer 1140 to form semiconductor mesa structures 1102 for individual micro-LEDs. As shown in FIG. 11B, the etching may include etching through p-type semiconductor layer 1140, active region 1130, and at least a portion of n-type semiconductor layer 1120. Thus, each semiconductor mesa structure 1102 may include p-type semiconductor layer 1140, active region 1130, and a portion of n-type semiconductor layer 1120. To perform the etching, an etch mask layer may be formed on p-type semiconductor layer 1140, and dry or wet etching may be performed from the side of p-type semiconductor layer 1140. Due to the etching from p-type semiconductor layer 1140, semiconductor mesa structure 1102 may have sidewalls that are inwardly tilted in the z direction. In some embodiments, semiconductor mesa structures 1102 may have a conical shape, a parabolic shape, a truncated pyramid shape, or another shape. In some embodiments, after the etching, sidewalls of the etched semiconductor mesa structures 1102 may be treated, for example, using KOH or an acid, to remove regions that may be damaged by high-energy ions during the dry etching.

FIG. 11C shows that micro-LED wafer 1100 may be further processed from the side of p-type semiconductor layer 1140 to form a wafer 1104 that includes an array of micro-LEDs. In the illustrated example, a passivation layer 1145 may be formed on sidewall surfaces of semiconductor mesa structures 1102, to electrically isolate semiconductor mesa structures 1102. Passivation layer 1145 may include a dielectric material, such as SiO₂, Al₂O₃, or Si₃N₄, or may include an undoped semiconductor material. A reflective metal layer 1150 (e.g., Al, Au, Ag, Cu, Ti, Ni, Pt, or a combination thereof) may be formed on passivation layer 1145 to optically isolate individual micro-LEDs and improve the light extraction efficiency. In some embodiments, reflective metal layer 1150 may fill gaps between semiconductor mesa structures 1102. In some embodiments, a dielectric material 1152 (e.g., SiO₂) may be deposited on reflective metal layer 1150 and regions between semiconductor mesa structures 1102. Passivation layer 1145, reflective metal layer 1150, and/or dielectric material 1152 may electrically and optically isolate individual micro-LEDs, and may be formed using suitable deposition techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), atomic-layer deposition (ALD), laser metal deposition (LIVID), or sputtering.

The top surfaces of semiconductor mesa structures 1102, reflective metal layer 1150, and/or dielectric material 1152 may be planarized, for example, using CMP techniques. A dielectric material 1160 (e.g., including SiO₂) may then be deposited on the planarized top surfaces. In some embodiments, before depositing dielectric material 1160, an ITO layer may be formed on the planarized top surfaces to make contact with p-type semiconductor layer 1140 of semiconductor mesa structures 1102. Back reflector and p-contacts 1162 may be formed in dielectric material 1160 and may contact p-type semiconductor layer 1140 of corresponding semiconductor mesa structures 1102. Back reflector and p-contacts 1162 may include, for example, Au, Ag, Al, Ti, Cu, Ni, ITO, or a combination thereof. Even though not shown in FIG. 11C, in some embodiments, one or more dielectric layers (e.g., including SiO₂) and metal interconnects (e.g., copper plugs or pads) may be formed on back reflector and p-contacts 1162. The one or more dielectric layers may include a bonding layer that includes metal bonding pads formed therein as described above with respect to, for example, FIG. 9B. In some embodiments, the bonding layer may include dielectric material 1160 and back reflector and p-contacts 1162 formed in dielectric material 1160.

Even though not shown in FIG. 11C, there may be a barrier layer between back reflector and p-contacts 1162 and dielectric material 1160. The barrier layer may include, for example, Ti, Ta, TiN, TaN, W, or a combination thereof, such as TiN/Ti, TaN/Ta, Ti/TiN, or Ta/TaN. The barrier layer may need to have a certain thickness in order to prevent the diffusion of the metal (e.g., copper) from back reflector and p-contacts 1162 to the dielectric material and semiconductor material. The bonding layer may need to be planarized to have a flat and smooth bonding surface for subsequent bonding. The planarization process (e.g., CMP) may cause rounding or trenches in dielectric material 1160 and/or the barrier layer at the interfaces between back reflector and p-contacts 1162 and dielectric material 1160 (or the barrier layer) due to different mechanical strengths (e.g., stiffnesses or hardness) of the different materials. The rounding or trenches in dielectric material 1160 and/or the barrier layer may reduce the contact area of the dielectric material at the bonding interface, and thus may reduce the bonding strength of the dielectric bonding.

FIG. 11D shows that wafer 1104 may be bonded to a backplane wafer 1106 in a hybrid bonding process. Backplane wafer 1106 may include a substrate 1170 with electrical circuits fabricated thereon. The electrical circuits may include digital and analog pixel drive circuits for driving individual micro-LEDs. A plurality of metal pads 1172 (e.g., copper or tungsten pads) may be formed in a dielectric layer 1174 (e.g., including SiO₂ or SiN). In some embodiments, each metal pad 1172 may be an electrode (e.g., anode or cathode) for a micro-LED. Even though FIG. 11D only shows metal pads 1172 formed in one dielectric layer 1174, backplane wafer 1106 may include metal interconnects formed in two or more dielectric material layers and one or more metal layers, as in many CMOS integrated circuits. Even though not shown in FIG. 11D, there may be a barrier layer between metal pads 1172 and dielectric layer 1174. The barrier layer may include, for example, Ti, Ta, TiN, TaN, W, or a combination thereof, such as TiN/Ti, TaN/Ta, Ti/TiN, or Ta/TaN. The barrier layer may need to have a certain thickness in order to prevent the diffusion of the metal (e.g., copper) from metal pads 1172 to the dielectric material and semiconductor material as described above. Backplane wafer 1106 may be planarized to have a flat and smooth bonding surface. In some cases, the planarization may cause rounding or trenches in dielectric layer 1174 and/or the barrier layer at the interfaces between metal pads 1172 and dielectric layer 1174 (or the barrier layer) due to different mechanical strengths (e.g., stiffnesses or hardness) of the different materials. The rounding or trenches in dielectric layer 1174 and/or the barrier layer may reduce the contact area of the dielectric material at the bonding interface, and thus may reduce the bonding strength of the dielectric bonding.

As described above with respect to, for example, FIGS. 9A-9D, the bonding surfaces of wafer 1104 and backplane wafer 1106 may be cleaned and activated before the bonding. Wafer 1104 may be turned upside down and brought into contact with backplane wafer 1106 such that dielectric layer 1174 and dielectric material 1160 may be in direct contact and may be bonded together due to the surface activation, with or without heat treatment. In some embodiments, a compression pressure may be applied to wafer 1104 and backplane wafer 1106 such that the bonding layers are pressed against each other. After the bonding of the dielectric materials, an annealing process may be performed at an elevated temperature to expand and bond the metal pads (e.g., back reflector and p-contacts 1162 and metal pads 1172) at the bonding surfaces.

FIG. 11E shows that, after the bonding of wafer 1104 and backplane wafer 1106, substrate 1110 of wafer 1104 may be removed, and a transparent conductive oxide (TCO) layer 1180 (e.g., such as an ITO layer) may be formed on the exposed n-type semiconductor layer 1120. TCO layer 1180 may form a common cathode for the micro-LEDs. In the illustrated example, non-native lenses 1190 may be fabricated in a dielectric material (e.g., SiN or SiO₂) or an organic material, and may be bonded to TCO layer 1180. In some embodiments, non-native lenses 1190 may be fabricated in a dielectric material layer deposited on TCO layer 1180. In some embodiments, native lenses may be fabricated in n-type semiconductor layer 1120, and the common cathode may be formed on the native lenses and/or may be the portion of n-type semiconductor layer 1120 that has not been etched (which may be heavily doped to reduce the resistance).

As described above, the internal quantum efficiency of an LED depends on the relative rates of competitive radiative (light producing) recombination and non-radiative (lossy) recombination that occur in the active region of the LED. Non-radiative recombination processes in the active region include Shockley-Read-Hall (SRH) recombination at defect sites and electron-electron-hole (eeh) and/or electron-hole-hole (ehh) Auger recombination. The Auger recombination is a non-radiative process involving three carriers, which affects all sizes of LEDs. The internal quantum efficiency of an LED may be determined by:

$\begin{array}{cc}\mathrm{IQE}=\frac{B{N}^2}{AN+B{N}^2+C{N}^3},& \left(2\right)\end{array}$

where A, B, and C are the rates of SRH recombination, bimolecular (radiative) recombination, and Auger recombination, respectively, and Nis the charge-carrier density (i.e., charge-carrier concentration) in the active region.

In micro-LEDs, because the lateral size of each micro-LED may be comparable to the minority carrier diffusion length, a larger proportion of the total active region may be within a distance less than the minority carrier diffusion length from the micro-LED sidewall surfaces where the defect density and the defect-induced non-radiative recombination rate may be high due to the abrupt ending of the lattice structure, chemical contamination, and/or structural damages (e.g., due to dry etch). Therefore, a larger proportion of the injected carriers may diffuse to the regions near the sidewall surfaces, where the carriers may be subjected to a higher SRH recombination rate. This may cause the efficiency of the micro-LED to decrease (in particular, at low current injection), cause the peak efficiency of the micro-LED to decrease, and/or cause the peak efficiency operating current to increase. Increasing the injected current may cause the efficiency of the micro-LED to drop due to the higher eeh or ehh Auger recombination rate at a higher current density, and may also cause spectral shift of the emitted light. As the physical sizes of micro-LEDs are further reduced, efficiency losses due to surface recombination near the etched sidewall facets that include surface imperfections may become much more significant.

In addition, the performance of micro-LED may be very sensitive to temperature. For example, the electron and hole concentration, electron mobility, operation current and voltage, and energy bandgap of a micro-LED may change with junction temperature. Non-radiative recombination and leakage current may also increase at high operational current densities and high temperatures. For example, Auger recombination may be a temperature-dependent source of non-radiative recombination and can contribute to efficiency droop at high-injection current conditions. SRH recombination from trap states is also temperature dependent. Therefore, the efficiencies of micro-LEDs may decrease to cause brightness decay as the device heats up. The junction temperature change may also cause an energy bandgap decrease and thus a color displacement that may affect the color quality of the micro-LED at high junction temperatures. If no effective thermal control technique is employed, there may be a temperature gradient within a micro-LED array, which may cause different brightness decay and color shifting at different micro-LEDs of the micro-LED array. In micro-LEDs with low efficiencies, a high percentage of the electrical power may be converted to heat to heat up the micro-LEDs. Thus, the devices performance of the micro-LEDs may significantly deteriorate due to the increase of the operating temperature if no effective thermal control technique is employed. Some structures and external cooling devices may be used to alleviate the temperature-dependent performance droop by reducing the operating temperature, including modifying device architectures and using external cooling devices. However, due to the constraints in the energy budget and the form factor of near-eye displays, active thermal solution for local temperature control may not be feasible for micro-LEDs used in near-eye displays.

The dielectric materials commonly used as insulation materials in micro-LEDs may include, for example, SiO₂, Si₃N₄, and Al₂O₃. SiO₂ has been widely used as the dielectric material in CMOS technology that is mature to a great extent. Therefore, SiO₂ is also widely used as the dielectric material in micro-LEDs that may be fabricated using processing techniques developed for or compatible with CMOS technology. However, the thermal conductivities of these dielectric materials, such as SiO₂, Si₃N₄, and Al₂O₃, are generally much lower compared with the semiconductor materials of the micro-LEDs, and thus may not be able to efficiently and rapidly dissipate heat generated in the active regions of micro-LEDs into the backplane to maintain a uniform temperature distribution among the micro-LEDs in a micro-LED array.

FIG. 12A includes a diagram 1200 showing the thermal conductivities of SiO₂ and AlN and the thermal resistances of micro-LED bonding layers including SiO₂ and AlN. The thermal conductivity of SiO₂ is generally about 1.2-1.3 W/(mK) for thin layers or about 1.4 W/(m·K) for bulk material. The thermal conductivity of amorphous Si₃N₄ may be comparable to or lower than that of SiO₂. The thermal conductivity of Al₂O₃ may be around 25-30 W/(m·K) at room temperature. In contrast, the thermal conductivity of AlN may be about 220 W/(m·K) or higher at room temperature, and may be in the range of 150-220 W/(m·K) or higher at temperatures between room temperature and about 450 K, which may be two orders of magnitude higher than that of SiO₂ and Si₃N₄, and may be comparable to the thermal conductivity of copper (e.g., about 230-400 W/(m·K)) and the thermal conductivity of aluminum (e.g., about 130-240 W/(m·K)) at room temperature. AlN may have a high thermal conductivity due to, for example, small atomic mass, strong interatomic bonds, and simple crystal structure. AlN may have a large energy bandgap, and thus may be used as an insulator.

The thermal resistance is a measure of resistance to heat flow through a given thickness of a material and may be determined by:

$\begin{array}{cc}{R}_{th}=\frac{L}{kA},& \left(3\right)\end{array}$

where A is the size of a thermal conductive material layer, L is the thickness of the thermal conductive material layer, and k is the thermal conductivity of the thermal conductive material. In the example shown in FIG. 12A, the thermal resistance of the bonding layers of a micro-LED device with a size about 4 mm×3 mm and a total thickness about 2×800 nm (including two bonding layers each having a thickness about 800 nm) is shown, where the dielectric material of the hybrid bonding layer is SiO₂ or AlN. As illustrated, by changing the dielectric material of the hybrid bonding layers from SiO₂ to AlN, the estimated thermal resistance of the hybrid bonding layers may be improved by two orders of magnitude or more.

FIG. 12B includes a table 1202 showing the thermal expansion coefficients (CTEs) of SiO₂, AlN, and some other materials (e.g., Si and GaN) that may be used in a micro-LED device. As illustrated, compared with the CTE of SiO₂ (e.g., about 0.56 ppm/° C.), the CTE of AlN (e.g., about 4.6 ppm/° C. at about 300° C.) is much closer to those of the Si backplane (e.g., about 2.6-3.3 ppm/° C.) and the epitaxial layers (e.g., about 3.2 ppm/° C. for GaN or about 5.2 ppm/° C. for GaInP). As a result, using AlN as the dielectric material can also reduce the CTE mismatch among the different materials of the micro-LED device.

According to certain embodiments, the low-thermal conductivity dielectric materials (e.g., SiO₂, SiN, and Al₂O₃) commonly used in the interconnect layers and/or bonding layers of existing micro-LED devices may be replaced by high-thermal conductivity dielectric materials, such as aluminum nitride (AlN), beryllium oxide (BeO), and boron nitride (BN). The AlN dielectric layers can help to efficiently and rapidly dissipate heat generated in the active regions of micro-LEDs into the backplane to retain a uniform temperature distribution among the micro-LEDs in a micro-LED array. Therefore, the AlN layers may behave as efficient heat spreading layers between the micro-LED array and drive circuits on the backplane, and thus may provide a passive thermal control solution for maintaining desired local temperatures. In addition, as described above, using AlN rather than SiO₂ may help mitigate the CTE mismatch among different materials in the micro-LED device, such as the silicon substrate, semiconductor epitaxial layers, and dielectric materials. Furthermore, due to the combability in the relevant processes, replacing dielectric materials such as SiO₂ with AlN may not negatively impact the downstream process flow.

FIG. 12C includes a graph 1204 showing an example of the expansion of metal bonding pads as a function of the annealing temperature. A curve 1210 in FIG. 12C shows an example of the increase of the height of the metal bonding pads in relation to the depth of the dishing of the metal bonding pads as a function of the annealing temperature in SiO₂-based hybrid bonding. A curve 1220 shows an example of the increase of the height of the metal bonding pads in relation to the depth of the dishing of the metal bonding pads as a function of the annealing temperature in AlN-based hybrid bonding. FIG. 12C shows that, compared with SiO₂-based hybrid bonding, AlN-based hybrid bonding may use lower annealing temperatures to expand the bonding pads and fill voids caused by the dishing. For example, results shown in FIG. 12C indicate that, in AlN-based hybrid bonding, the annealing temperature to fill the voids caused by dishing may be reduced by about 12.5° C. in comparison with SiO₂-based hybrid bonding.

In addition, the intrinsic stress inside an AlN layer can be tuned, such that desired wafer bowing (e.g., low or similar bowing) of the wafers to be bonded may be achieved, which may make the downstream processes, such as wafer alignment and wafer-to-wafer hybrid bonding, easier to perform. Furthermore, AlN may have a much higher hardness (e.g., about 18 GPa) than SiO₂ (e.g., about 10 GPa), and a higher fracture strength (e.g., about 1.54 GPa) than SiO₂ (e.g., about 0.81 GPa). Thus, AlN layers used as the bonding layers may have lower rounding and/or trenches in areas adjacent to the metal interconnects after the planarization of the bonding layers. Therefore, the dielectric bonding area and bonding strength at the AlN-AlN bonding interface may be larger than those at the SiO₂-SiO₂ bonding interface. The surface roughness of AlN can be comparable to the surface roughness of SiO₂, such as a few angstroms, and thus the AlN-AlN bonding and the SiO₂-SiO₂ bonding may have comparable bonding quality. A barrier layer may not need to be used between the metal interconnects and the AlN material in the bonding layer to prevent the diffusion of metal atoms into the AlN material and the semiconductor material. Additionally, in some micro-LED wafers, such as a GaN-on-Si wafer, an AlN layer may often be grown on the silicon substrate as the seed layer (or buffer layer) during the epitaxy growth. In some embodiments, this AlN seed layer may be used as the bonding layer and metal bonding pads can be formed in this AlN seed layer, and thus a deposition process (e.g., a spluttering process) may not be needed to deposit the AlN dielectric layer for hybrid bonding, which may simplify the downstream process flow.

FIG. 13A illustrates an example of a micro-LED device 1300 according to certain embodiments. In the illustrated example, micro-LED device 1300 may include a micro-LED wafer bonded to or otherwise formed on a backplane wafer. The backplane wafer may include a substrate 1370 (e.g., a silicon substrate) including pixel drive circuits formed thereon. The pixel drive circuits may include CMOS circuits, such as CMOS transistors. The backplane wafer may also include one or more dielectric layers (e.g., AlN layers) and metal interconnects (e.g., copper or tungsten pads or plugs) formed therein. In the illustrated example, the backplane wafer may include a bonding layer that includes an AlN layer 1372 and metal interconnects 1374 (e.g., copper pads or plugs) formed therein. In some embodiments, the internal stress of AlN layer 1372 may be tuned to achieve desired wafer bowing of the backplane wafer before bonding.

The micro-LED wafer may include an array of micro-LEDs formed in an epitaxial layer stack. The epitaxial layer stack may include a first semiconductor layer 1310 (e.g., an n-type or p-type semiconductor layer), active layers 1320 (e.g., including quantum well layers and quantum barrier layers), and a second semiconductor layer 1330 (e.g., a p-type or n-type semiconductor layer). The epitaxial layer stack may be etched to form an array of semiconductor mesa structures. A passivation layer 1340 may be formed on sidewalls of the semiconductor mesa structures. Passivation layer 1340 may include, for example, a dielectric layer (e.g., including SiO₂, SiN, and Al₂O₃) or an undoped semiconductor layer. A reflective metal layer 1350 (e.g., including Al, Cu, Au, Ag, Ti, or a combination) may be deposited on passivation layer 1340. In some embodiments, reflective metal layer 1350 may fill gaps between the semiconductor mesa structures. In some embodiments, a high-thermal conductivity dielectric material 1352 (e.g., including AlN) may be deposited in regions between the semiconductor mesa structures. The micro-LED wafer may include one or more dielectric layers (e.g., AlN layers) formed on the semiconductor mesa structures and high-thermal conductivity dielectric material 1352. Metal interconnects (e.g., copper or tungsten pads or plugs) may be formed in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1360 and metal interconnects 1362 (e.g., copper pads or plugs) formed therein. In some embodiments, the internal stress of AlN layer 1360 may be tuned to achieve desired wafer bowing of the micro-LED wafer. In the illustrated example, metal interconnects 1362 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for the micro-LEDs.

The micro-LED wafer may be bonded to the backplane wafer by, for example, bonding the bonding layer that includes AlN layer 1360 and metal interconnects 1362 to the bonding layer that includes AlN layer 1372 and metal interconnects 1374, using a hybrid wafer-to-wafer bonding process described above and below. For example, the two bonding layers may be cleaned and activated by, for example, an ion (e.g., plasma) beam or a fast atom (e.g., Ar) beam. Ar sputtering may also remove the Cu oxide layer. In some embodiments, the backplane wafer and the micro-LED wafer may be rinsed with deionized water and blown dry using nitrogen gas (N₂). The activated surface may be atomically clean and reactive for formation of direct bonds between wafers when they are brought into contact, for example, at room temperature. In some embodiments, compressive force may be applied to the two bonding layers such that the two bonding layers may be pressed against each other. Due to the surface activation, the AlN in AlN layer 1360 and the AlN in AlN layer 1372 may react and form chemical bonds between them because the surface atoms may have dangling bonds and may be in unstable energy states after the activation. Thus, the AlN in AlN layer 1360 and the AlN in AlN layer 1372 may be bonded together by van der Waals attractions, with or without heat treatment or pressure. During annealing, AlN layer 1360 that is in contact with AlN layer 1372 may strengthen the bonds through a two-step condensation reaction. The annealing may also cause metal interconnects 1362 and 1374 to expand such that metal interconnects 1362 and 1374 may be in contact and may form direct metallic bonds at the activated surfaces.

After the bonding, the substrate of the micro-LED wafer may be removed and a transparent conductive oxide (TCO) layer 1380 (e.g., such as an ITO layer) may be formed on first semiconductor layer 1310. TCO layer 1380 may form a common electrode (e.g., a common cathode or a common anode) for the micro-LEDs. In the illustrated example, non-native lenses 1390 may be fabricated in a dielectric material (e.g., SiN or SiO2), and may be bonded to TCO layer 1380. In some embodiments, non-native lenses 1390 may be fabricated in a dielectric material deposited on TCO layer 1380. In some embodiments, native lenses may be fabricated in first semiconductor layer 1310, and the common electrode may be formed on the native lenses and/or may be the portion of first semiconductor layer 1310 that has not been etched (which may be heavily doped to reduce the resistance).

In micro-LED device 1300, the bonding layers may have high thermal conductivities that may be comparable to the thermal conductivities of the semiconductor materials and metal materials. The material that fills gaps between the semiconductor mesa structures may also include metals or a high-thermal conductivity dielectric material (e.g., AlN). Therefore, heat generated in the semiconductor mesa structures may be more efficiently dissipated to the backplane wafer (which may include a heat sink and/or a heat control/recycle structure), thereby maintaining a low local temperature in the semiconductor mesa structures. In addition, the CTEs of the materials may be better matched, and thus processing the wafers at elevated temperatures (e.g., for annealing) and cooling the wafers may not cause damages or bowing to the micro-LED device. As described above, a barrier layer (e.g., including Ti, Ta, TiN, TaN, W, or a combination thereof, such as such as TiN/Ti, TaN/Ta, Ti/TiN, or Ta/TaN) may not need to be used between AlN layer 1360 and metal interconnects 1362, or between AlN layer 1372 and metal interconnects 1374. Furthermore, AlN may have a higher hardness or stiffness than SiO₂, and thus may have lower rounding and/or trenches after the planarization of the bonding layers, such that the bonding area and bonding strength of the dielectric bonding between AlN layer 1360 and AlN layer 1372 may be improved over devices with SiO₂ in the bonding layers.

FIG. 13B illustrates another example of a micro-LED device 1301 according to certain embodiments. In the illustrated example, micro-LED device 1301 may include a micro-LED wafer bonded to a backplane wafer. The backplane wafer may include a substrate 1311 (e.g., a silicon substrate) including pixel drive circuits formed thereon as described above. The backplane wafer may also include one or more dielectric layers and metal interconnects formed therein. In the illustrated example, the backplane wafer may include a bonding layer that includes an AlN layer 1321 and metal interconnects 1331 (e.g., copper pads or plugs).

The micro-LED wafer may include an array of micro-LEDs 1361 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1361 may include a mesa structure with sidewalls tilted inwardly in the light-emitting direction (e.g., the z direction). Even though not shown in FIG. 13B, each micro-LED 1361 may include a passivation layer and a reflector layer (e.g., including Al, Cu, Au, Ag, Ti, or a combination) on sidewalls of the mesa structure. Regions 1371 between micro-LEDs 1361 may be filled with, for example, a metal (e.g., Al or Cu) or a high-thermal conductivity dielectric material (e.g., AlN). The micro-LED wafer may also include one or more dielectric layers (e.g., AlN layers) and metal interconnects (e.g., copper or tungsten pads or plugs) in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1341 and metal interconnects 1351 (e.g., copper pads or plugs). In the illustrated example, metal interconnects 1351 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for micro-LEDs 1361. Micro-LED device 1301 may also include a common electrode (e.g., an ITO layer, not shown in FIG. 13B) for micro-LEDs 1361, and an array of micro-lenses 1381 aligned with the array of micro-LEDs 1361, where the array of micro-lenses 1381 may be separated from the array of micro-LEDs 1361 by a layer 1391 that may include a semiconductor material (e.g., a semiconductor epitaxial layer, such as an n-doped GaN layer) or a dielectric material (e.g., SiO₂, SiN, Al₂O₃, or AlN).

Micro-LED device 1301 may be fabricated by singulating micro-LEDs before bonding or after bonding as described above with respect to FIGS. 8A-11E. In one example, micro-LED device 1301 may be fabricated by depositing a first solid metal layer on the micro-LED wafer, depositing a second solid metal layer on the backplane wafer, bonding the micro-LED wafer to the backplane wafer by alignment-free metal-to-metal bonding of the first solid metal layer and the second solid metal layer, removing the substrate of the micro-LED wafer, etching through the epitaxial layer stack and the two solid metal layers to singulate individual micro-LEDs 1361 and metal interconnects 1331 and 1351, forming passivation layers and sidewall reflector layers on individual micro-LEDs 1361, depositing AlN into etched regions between individual micro-LEDs 1361 to form AlN layers 1321 and 1341, depositing AlN and/or another material in regions 1371, depositing a TCO layer (e.g., an ITO layer) on top of micro-LEDs 1361 for use as a common electrode for micro-LEDs 1361, depositing dielectric layer 1391, and forming (e.g., bonding or etching) micro-lenses 1381 as described above.

FIG. 13C illustrates another example of a micro-LED device 1306 according to certain embodiments. In the illustrated example, micro-LED device 1306 may include a micro-LED wafer bonded to a backplane wafer. The backplane wafer may include a substrate 1316 (e.g., a silicon substrate) including pixel drive circuits formed thereon as described above. The backplane wafer may also include one or more dielectric layers and metal interconnects formed therein. In the illustrated example, the backplane wafer may include a bonding layer that includes an AlN layer 1326 and metal interconnects 1336 (e.g., copper pads or plugs).

The micro-LED wafer may include an array of micro-LEDs 1366 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1366 may include a mesa structure with sidewalls tilted inwardly in the light-emitting direction (e.g., the z direction). Even though not shown in FIG. 13C, each micro-LED 1366 may include a passivation layer and a reflector layer (e.g., including Al, Cu, Au, Ag, Ti, or a combination) on sidewalls of the mesa structure. Regions 1376 between micro-LEDs 1366 may be filled with, for example, a metal (e.g., Al or Cu) or a high-thermal conductivity dielectric material (e.g., AlN). The micro-LED wafer may also include one or more dielectric layers (e.g., AlN layers) and metal interconnects (e.g., copper or tungsten pads or plugs) in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1346 and metal interconnects 1356 (e.g., copper pads or plugs). In the illustrated example, metal interconnects 1356 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for micro-LEDs 1366. Micro-LED device 1306 may also include a common electrode (e.g., an ITO layer, not shown in FIG. 13C) for micro-LEDs 1366, and an array of micro-lenses 1386 aligned with the array of micro-LEDs 1366, where the array of micro-lenses 1386 may be close to the array of micro-LEDs 1366. Micro-LED device 1306 may be fabricated using processes similar to the processes for fabricating micro-LED device 1301.

FIG. 13D illustrates another example of a micro-LED device 1303 according to certain embodiments. In the illustrated example, micro-LED device 1303 may include a micro-LED wafer bonded to a backplane wafer. The backplane wafer may include a substrate 1313 (e.g., a silicon substrate) including pixel drive circuits formed thereon as described above. The backplane wafer may also include one or more dielectric layers and metal interconnects formed therein. In the illustrated example, the backplane wafer may include a bonding layer that includes an AlN layer 1323 and metal interconnects 1333 (e.g., copper pads or plugs).

The micro-LED wafer may include an array of micro-LEDs 1363 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1363 may include a mesa structure with sidewalls tilted outwardly in the light-emitting direction (e.g., the z direction). Even though not shown in FIG. 13D, each micro-LED 1363 may include a passivation layer and a reflector layer (e.g., including Al, Cu, Au, Ag, Ti, or a combination) on sidewalls of the mesa structure. Regions 1373 between micro-LEDs 1363 may be filled with, for example, a metal (e.g., Al or Cu) or a high-thermal conductivity dielectric material (e.g., AlN). The micro-LED wafer may also include one or more dielectric layers (e.g., AlN layers) and metal interconnects (e.g., copper or tungsten pads or plugs) in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1343 and metal interconnects 1353 (e.g., copper pads or plugs). In the illustrated example, metal interconnects 1353 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for micro-LEDs 1363. Micro-LED device 1303 may also include a common electrode (e.g., an ITO layer, not shown in FIG. 13D) for micro-LEDs 1363, and an array of micro-lenses 1383 aligned with the array of micro-LEDs 1363, where the array of micro-lenses 1383 may be separated from the array of micro-LEDs 1363 by a layer 1393 that may include a semiconductor material (e.g., a semiconductor epitaxial layer, such as an n-doped GaN layer) or a dielectric material (e.g., SiO₂, SiN, Al₂O₃, or AlN).

Micro-LED device 1303 may be fabricated by singulating micro-LEDs 1363 before or after bonding the micro-LED wafer to the backplane wafer as described above with respect to FIGS. 8A-11E. In one example, micro-LED device 1303 may be fabricated using a process similar to the process described above with respect to FIGS. 11A-11E or described below with respect to FIGS. 14A-14D.

FIG. 13E illustrates another example of a micro-LED device 1307 according to certain embodiments. In the illustrated example, micro-LED device 1307 may include a micro-LED wafer bonded to a backplane wafer. The backplane wafer may include a substrate 1317 (e.g., a silicon substrate) including pixel drive circuits formed thereon as described above. The backplane wafer may also include one or more dielectric layers and metal interconnects formed therein. In the illustrated example, the backplane wafer may include a bonding layer that includes an AlN layer 1327 and metal interconnects 1337 (e.g., copper pads or plugs).

The micro-LED wafer may include an array of micro-LEDs 1367 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1367 may include a mesa structure with sidewalls tilted outwardly in the light-emitting direction (e.g., the z direction). Even though not shown in FIG. 13E, each micro-LED 1367 may include a passivation layer and a reflector layer (e.g., including Al, Cu, Au, Ag, Ti, or a combination) on sidewalls of the mesa structure. Regions 1377 between micro-LEDs 1367 may be filled with, for example, a metal (e.g., Al or Cu) or a high-thermal conductivity dielectric material (e.g., AlN). The micro-LED wafer may also include one or more dielectric layers (e.g., AlN layers) and metal interconnects (e.g., copper or tungsten pads or plugs) in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1347 and metal interconnects 1357 (e.g., copper pads or plugs). In the illustrated example, metal interconnects 1357 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for micro-LEDs 1367. Micro-LED device 1307 may also include a common electrode (e.g., an ITO layer, not shown in FIG. 13E) for micro-LEDs 1367, and an array of micro-lenses 1387 aligned with the array of micro-LEDs 1367, where the array of micro-lenses 1387 may be close to the array of micro-LEDs 1367.

Micro-LED device 1307 may be fabricated by singulating micro-LEDs 1367 before or after bonding the micro-LED wafer to the backplane wafer as described above with respect to FIGS. 8A-11E. In one example, micro-LED device 1307 may be fabricated using a process similar to the process described above with respect to FIGS. 11A-11E or the process described below with respect to FIGS. 14A-14D.

FIG. 13F illustrates another example of a micro-LED device 1305 according to certain embodiments. In the illustrated example, micro-LED device 1305 may include a micro-LED wafer bonded to a backplane wafer. Micro-LED device 1305 may be fabricated by singulating the micro-LEDs before or after bonding the micro-LED wafer to the backplane wafer as described above with respect to FIGS. 8A-11E, 13B, and 13D or described below with respect to

FIGS. 14A-14D. The backplane wafer may include a substrate 1315 (e.g., a silicon substrate) including pixel drive circuits formed thereon as described above. The backplane wafer may also include one or more dielectric layers and metal interconnects formed therein. In the illustrated example, the backplane wafer may include a bonding layer that includes an AlN layer 1325 and metal interconnects 1335 (e.g., copper pads or plugs).

The micro-LED wafer may include an array of micro-LEDs 1365 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1365 may include a mesa structure with vertical. Even though not shown in FIG. 13F, each micro-LED 1365 may include a passivation layer and a reflector layer (e.g., including Al, Cu, Au, Ag, Ti, or a combination) on sidewalls of the mesa structure. Regions 1375 between micro-LEDs 1365 may be filled with, for example, a metal (e.g., Al or Cu) or a high-thermal conductivity dielectric material (e.g., AlN). The micro-LED wafer may also include one or more dielectric layers (e.g., AlN layers) and metal interconnects (e.g., copper or tungsten pads or plugs) in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1345 and metal interconnects 1355 (e.g., copper pads or plugs). In the illustrated example, metal interconnects 1355 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for micro-LEDs 1365. Micro-LED device 1305 may also include a common electrode (e.g., an ITO layer, not shown in FIG. 13F) for micro-LEDs 1365, and an array of micro-lenses 1385 aligned with the array of micro-LEDs 1365, where the array of micro-lenses 1385 may be separated from the array of micro-LEDs 1365 by a layer 1395 that may include a semiconductor material (e.g., a semiconductor epitaxial layer, such as an n-doped GaN layer) or a dielectric material (e.g., SiO₂, SiN, Al₂O₅, or AlN).

FIG. 13G illustrates another example of a micro-LED device 1308 according to certain embodiments. In the illustrated example, micro-LED device 1308 may include a micro-LED wafer bonded to a backplane wafer. Micro-LED device 1308 may be fabricated by singulating the micro-LEDs before or after bonding the micro-LED wafer to the backplane wafer as described above with respect to FIGS. 8A-11E, 13B, and 13D or described below with respect to FIGS. 14A-14D. The backplane wafer may include a substrate 1318 (e.g., a silicon substrate) including pixel drive circuits formed thereon as described above. The backplane wafer may also include one or more dielectric layers and metal interconnects formed therein. In the illustrated example, the backplane wafer may include a bonding layer that includes an AlN layer 1328 and metal interconnects 1338 (e.g., copper pads or plugs).

The micro-LED wafer may include an array of micro-LEDs 1368 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1368 may include a mesa structure with vertical. Even though not shown in FIG. 13G, each micro-LED 1368 may include a passivation layer and a reflector layer (e.g., including Al, Cu, Au, Ag, Ti, or a combination) on sidewalls of the mesa structure. Regions 1378 between micro-LEDs 1368 may be filled with, for example, a metal (e.g., Al or Cu) or a high-thermal conductivity dielectric material (e.g., AlN). The micro-LED wafer may also include one or more dielectric layers (e.g., AlN layers) and metal interconnects (e.g., copper or tungsten pads or plugs) in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1348 and metal interconnects 1358 (e.g., copper pads or plugs). In the illustrated example, metal interconnects 1358 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for micro-LEDs 1368. Micro-LED device 1308 may also include a common electrode (e.g., an ITO layer, not shown in FIG. 13G) for micro-LEDs 1368, and an array of micro-lenses 1388 aligned with the array of micro-LEDs 1368, where the array of micro-lenses 1388 may be close to the array of micro-LEDs 1368.

FIGS. 14A-14D illustrate an example of a method of fabricating a micro-LED device according to certain embodiments. FIG. 14A shows a backplane wafer 1400 and a micro-LED wafer 1402. As described above, backplane wafer 1400 may include drive circuits 1410 and an AlN layer 1420 deposited on drive circuits 1410. AlN layer 1420 may be deposited on drive circuits 1410 by, for example, pre-cleaning backplane wafer 1400 using the Radio Corporation of America (RCA) cleaning method to remove any organic and metallic contaminants, and then sputtering aluminum on backplane wafer 1400 in reactive N₂ atmosphere. In some embodiments, an annealing process may be performed at an elevated temperature (e.g., about 450° C.) to densify AlN layer 1420, allow outgassing of the incorporated gases, and avoid voids formation at the bonding interface in the subsequent processes. Micro-LED wafer 1402 may include an array of mesa structures 1440 and electrical and optical insulation materials 1430 between mesa structures 1440. In some embodiments, electrical and optical insulation materials 1430 may include a high-thermal conductivity dielectric material, such as AlN. An AlN layer 1450 may be deposited on micro-LED wafer 1402 in processes similar to the processes for depositing AlN layer 1420.

FIG. 14B shows that AlN layer 1420 and AlN layer 1450 may be etched to form trenches 1422 and 1452, respectively. Trenches 1422 and 1452 may be used to form metal bonding pads. FIG. 14C shows that metal materials 1424 and 1454 (e.g., including Cu) may be deposited in trenches 1422 and 1452 and on AlN layer 1420 and AlN layer 1450. As described above, in some embodiments, a barrier layer may be formed on sidewalls of trenches 1422 and 1452 before the deposition of metal materials 1424 and 1454 in trenches 1422 and 1452. In some embodiments, the barrier layer may not be needed. After the deposition of metal materials 1424 and 1454, the bonding surfaces of backplane wafer 1400 and micro-LED wafer 1402 may be planarized, for example, using CMP. As described above, AlN may have a higher hardness or stiffness than SiO₂, and thus there may be lower rounding and/or trenches in AlN layer 1420 and AlN layer 1450 after the planarization, such that the bonding area and bonding strength of the dielectric bonding between AlN layer 1420 and AlN layer 1450 may be increased, compared with bonding layers with SiO₂ as the dielectric material. The planarized bonding surfaces of backplane wafer 1400 and micro-LED wafer 1402 may be cleaned after the planarization.

FIG. 14D shows that the planarized bonding surfaces of backplane wafer 1400 and micro-LED wafer 1402 may be activated by one or more plasma etching processes, using, for example, O₂, Ar, and SF₆, and may be cleaned using, for example, deionized water and blown dry with N₂. After the activation and cleaning, backplane wafer 1400 and micro-LED wafer 1402 may be brought together such that AlN layer 1420 may contact AlN layer 1450 to form dielectric bonds at room temperature. The bonded wafer stack may be annealed, for example, at an elevated temperature (e.g., >150° C. or 200° C.), to bond metal materials 1424 and 1454 at the bonding interface.

FIGS. 15A-15G illustrate examples of micro-LED devices according to certain embodiments. FIG. 15A illustrates an example of a micro-LED device 1500 that may be fabricated using the processes described above with respect to, for example, FIGS. 14A-14D. In the illustrated example, micro-LED device 1500 may include drive circuits 1510 bonded to an array of micro-LEDs 1550 using a bonding layer 1520 and a bonding layer 1560. Bonding layer 1520 and bonding layer 1560 may include AlN layers and metal interconnects 1530 and 1570 formed in the AlN layers. The array of micro-LEDs 1550 may be electrically and optically isolated by insulation materials 1540, which may include a metal and/or a high-thermal conductivity dielectric material, such as AlN.

FIG. 15B illustrates another example of a micro-LED device 1502 according to certain embodiments. In the illustrated example, micro-LED device 1502 may include a backplane wafer bonded to a micro-LED wafer. The backplane wafer may include drive circuits 1512, one or more AlN layers 1522 including metal interconnects 1532 formed therein, and a bonding layer 1592 including a SiO₂ layer and metal interconnects 1532 formed therein. The micro-LED wafer may include an array of micro-LEDs 1552 electrically and optically isolated by insulation materials 1542, one or more AlN layers 1562 including metal interconnects 1572 formed therein, and a bonding layer 1582 including a SiO₂ layer and metal interconnects 1572 formed therein. Insulation materials 1542 may include a metal and/or a high-thermal conductivity dielectric material, such as AlN. The backplane wafer may be bonded to the micro-LED wafer through SiO₂-SiO₂ bonding of bonding layer 1582 and bonding layer 1592.

FIG. 15C illustrates another example of a micro-LED device 1504 according to certain embodiments. In the illustrated example, micro-LED device 1504 may include a backplane wafer bonded to a micro-LED wafer. The backplane wafer may include drive circuits 1514, one or more SiO₂ layers 1524 including metal interconnects 1534 formed therein, and a bonding layer 1594 including an AlN layer and metal interconnects 1534 formed therein. The micro-LED wafer may include an array of micro-LEDs 1554 electrically and optically isolated by insulation materials 1544, one or more SiO₂ layers 1564 including metal interconnects 1574 formed therein, and a bonding layer 1584 including an AlN layer and metal interconnects 1574 formed therein. Insulation materials 1544 may include a metal and/or a high-thermal conductivity dielectric material, such as AlN. The backplane wafer may be bonded to the micro-LED wafer through AlN-AlN bonding of bonding layer 1584 and bonding layer 1592.

FIG. 15D illustrates yet another example of a micro-LED device 1506 according to certain embodiments. In the illustrated example, micro-LED device 1506 may include a backplane wafer bonded to a micro-LED wafer. The backplane wafer may include drive circuits 1516, one or more SiO₂ layers 1526 including metal interconnects 1536 formed therein, and a bonding layer 1596 including an AN layer and metal interconnects 1536 formed therein. The micro-LED wafer may include an array of micro-LEDs 1556 electrically and optically isolated by insulation materials 1546, and a bonding layer 1566 including an AlN layer and metal interconnects 1576 formed therein. Insulation materials 1546 may include a metal and/or a high-thermal conductivity dielectric material, such as AlN. The backplane wafer may be bonded to the micro-LED wafer through AlN-AlN bonding of bonding layer 1566 and bonding layer 1596.

FIG. 15E illustrates yet another example of a micro-LED device 1501 according to certain embodiments. In the illustrated example, micro-LED device 1501 may include a backplane wafer bonded to a micro-LED wafer. The backplane wafer may include drive circuits 1511, one or more AlN layers 1521 including metal interconnects 1531 formed therein, and a bonding layer 1591 including a SiO₂ layer and metal interconnects 1531 formed therein. The micro-LED wafer may include an array of micro-LEDs 1551 electrically and optically isolated by insulation materials 1541, and a bonding layer 1561 including a SiO₂ layer and metal interconnects 1571 formed therein. Insulation materials 1541 may include a metal and/or a high-thermal conductivity dielectric material, such as AlN. The backplane wafer may be bonded to the micro-LED wafer through SiO₂-based hybrid bonding of bonding layer 1561 and bonding layer 1591.

FIG. 15F illustrates another example of a micro-LED device 1503 according to certain embodiments. In the illustrated example, micro-LED device 1503 may include a backplane wafer bonded to a micro-LED wafer. The backplane wafer may include drive circuits 1513, and a bonding layer 1523 including one or more AlN layers and metal interconnects 1533 formed therein. The micro-LED wafer may include an array of micro-LEDs 1553 electrically and optically isolated by insulation materials 1543, one or more SiO₂ layers 1563 including metal interconnects 1573 formed therein, and a bonding layer 1593 including an AlN layer and metal interconnects 1573 formed therein. Insulation materials 1543 may include a metal and/or a high-thermal conductivity dielectric material, such as AlN. The backplane wafer may be bonded to the micro-LED wafer through AlN-based hybrid bonding of bonding layer 1593 and bonding layer 1523.

FIG. 15G illustrates another example of a micro-LED device 1505 according to certain embodiments. In the illustrated example, micro-LED device 1505 may include a backplane wafer bonded to a micro-LED wafer. The backplane wafer may include drive circuits 1515, and a bonding layer 1525 including one or more SiO₂ layers and metal interconnects 1535 formed therein. The micro-LED wafer may include an array of micro-LEDs 1555 electrically and optically isolated by insulation materials 1545, one or more AlN layers 1565 including metal interconnects 1575 formed therein, and a bonding layer 1595 including a SiO₂ layer and metal interconnects 1575 formed therein. Insulation materials 1545 may include a metal and/or a high-thermal conductivity dielectric material, such as AlN. The backplane wafer may be bonded to the micro-LED wafer through SiO₂-based hybrid bonding of bonding layer 1595 and bonding layer 1525.

FIG. 16 shows a comparison of the total thermal resistance of micro-LEDs with SiO₂ hybrid bonding layers and the total thermal resistance of micro-LEDs with AlN hybrid bonding layers. The micro-LEDs may include an n-contact layer (e.g., an ITO layer) with a thickness about 115 nm, an n-type semiconductor layer with a thermal conductivity about 55 W/(m·K) and a thickness about 1.4 μm, an active region with a thermal conductivity about 33 W/(m·K) and a thickness about 50 nm, and a p-type semiconductor layer with a thermal conductivity about 55 W/(m·K) and a thickness about 300 nm. The micro-LEDs with SiO₂ hybrid bonding layers may include Cu interconnects, and a total thickness of the SiO₂ hybrid bonding layers may be about 1.6 μm, where the thermal resistance of the SiO₂ hybrid bonding layers may be about 86% of the total thermal resistance of the micro-LED device (excluding the drive circuits of the backplane wafer). In contrast, in the micro-LEDs with AlN hybrid bonding layers that include Cu interconnects and have a total thickness about 1.6 μm, the thermal resistance of the AlN hybrid bonding layers may only be about 33% of the total thermal resistance of the micro-LED device (excluding the drive circuits of the backplane wafer). Therefore, the AlN hybrid bonding layers can significantly reduce the thermal resistance of the micro-LED devices.

As described above, other high-thermal conductivity dielectric materials may also be used in micro-LED devices to efficiently and rapidly dissipate heat generated in the active regions of micro-LEDs. For example, beryllium oxide (BeO) and boron nitride (BN), such as amorphous boron nitride (a-BN), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN), or Wurtzite boron nitride (w-BN), may have high thermal conductivity and high energy bandgap, and thus may be used as electrical insulating materials in micro-LED devices.

FIG. 17 includes a flowchart 1700 illustrating an example of a process of fabricating a micro-LED device according to certain embodiments. It is noted that the operations illustrated in FIG. 17 provide particular processes for fabricating micro-LED devices. Other sequences of operations can also be performed according to alternative embodiments. For example, alternative embodiments may perform the operation in a different order. Moreover, the individual operations illustrated in FIG. 17 can include multiple sub-operations that can be performed in various sequences as appropriate for the individual operation. Furthermore, some operations can be added or removed depending on the particular applications. In some implementations, two or more operations may be performed in parallel. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

Operations in block 1710 of flowchart 1700 may include obtaining a micro-LED wafer that includes an array of micro-LEDs. The array of micro-LEDs may include an array of semiconductor mesa structures and electrical and optical insulation materials between the semiconductor mesa structures of the array of semiconductor mesa structures. The array of semiconductor mesa structures may be etched in an epitaxial layer stack grown on a substrate. The epitaxial layer stack may include a p-type semiconductor layer, an active region that includes one or more quantum well layers and two or more quantum barrier layers, and an n-type semiconductor layer. Each micro-LED of the array of micro-LEDs may include a semiconductor mesa structure of the array of semiconductor mesa structures, a passivation layer on sidewalls of the semiconductor mesa structure, and a reflective metal layer on the passivation layer. In some embodiments, the reflective metal layer may fill regions between the semiconductor mesa structures of the array of semiconductor mesa structures. In some embodiments, regions between the semiconductor mesa structures of the array of semiconductor mesa structures may be filled with a high-thermal conductivity dielectric material, such as AlN. In some embodiments, the array of micro-LEDs may include a back reflector and contact layer on the semiconductor mesa structures. The back reflector and contact layer may be in contact with the p-type semiconductor layer or the n-type semiconductor layer, and may include, for example, Au, Ag, Al, Ti, Cu, Ni, ITO, or a combination thereof

Optional operations in block 1720 may include depositing an AlN bonding layer on the array of micro-LEDs on the micro-LED wafer. For example, the micro-LED wafer may be pre-cleaned using the RCA cleaning method to remove any organic and metallic contaminants, and then the AlN bonding layer may be deposited on the array of micro-LEDs by sputtering aluminum in reactive N₂ atmosphere. In some embodiments, an annealing process may be performed at an elevated temperature to densify the AlN bonding layer. In some embodiments, an AlN layer may be grown on a substrate and used as a seed layer (or buffer layer) during the epitaxy growth. This AlN seed layer may be used as the AlN bonding layer, and metal bonding pads can be formed in this AlN seed layer, such that a deposition process (e.g., a spluttering process) may not be needed to deposit the AlN bonding layer for the hybrid bonding.

Operations in block 1730 may include forming metal bonding pads in the AlN bonding layer. For example, the AlN bonding layer may be etched to form trenches in the AlN bonding layer, and a metal material (e.g., Cu or W) may be deposited in the trenches and on the MN bonding layer. In some embodiments, a barrier layer may be formed on sidewalls of the trenches before the deposition of the metal material. The metal material in the trenches may be used as the metal bonding pads for hybrid bonding.

Operations in block 1740 may include planarizing and activating the AlN bonding layer. For example, the AlN bonding layer may be planarized using CMP, to remove the metal material on the AlN bonding layer and form a flat, smooth surface at the bonding surface of the AlN bonding layer. The planarized bonding surface of the AlN bonding layer may be activated by one or more plasma etching processes, using, for example, O₂, Ar, and SF₆, and may be cleaned using, for example, deionized water and blown dry with N₂.

Operations in block 1715 of flowchart 1700 may include obtaining a backplane wafer including LED drive circuits formed thereon. The backplane wafer may include one or more dielectric layers and metal interconnects formed in the dielectric layers. At block 1725, an AlN bonding layer may be deposited on the backplane wafer in operations similar to the operations of block 1720. At block 1735, metal bonding pads may be formed in the AlN bonding layer deposited on the backplane wafer using operations similar to the operations of block 1730. At block 1745, the AlN bonding layer on the backplane wafer may be planarized and activated using operations similar to the operations of block 1740.

In block 1750, the AlN bonding layer of the micro-LED wafer may be bonded to the AlN bonding layer of the backplane wafer, for example, at room temperature. For example, the backplane wafer and the micro-LED wafer may be brought together such that the AlN bonding layer on the micro-LED wafer may contact the AlN bonding layer on the backplane wafer, to form AlN-AlN bonding at room temperature. In some embodiments, the backplane wafer may be compressed against the micro-LED wafer.

In block 1760, the bonded wafer stack may be annealed at an elevated temperature to cause the expansion of the metal bonding pads, such that the metal bonding pads of the micro-LED wafer may contact the metal bonding pads of the backplane wafer to form metal-metal bonds. After the annealing, the substrate of the micro-LED wafer may be removed, a transparent common cathode or anode (e.g., an ITO layer) may be formed on the exposed semiconductor layer (e.g., the n-type semiconductor layer or the p-type semiconductor layer). In some embodiments, light extraction structures, such as micro-lenses or gratings, may be formed on or bonded to the transparent common cathode or anode.

Embodiments disclosed herein may be used to implement components of an artificial reality system or may be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, for example, a virtual reality, an augmented reality, a mixed reality, a hybrid reality, or some combination and/or derivatives thereof. Artificial reality content may include completely generated content or generated content combined with captured (e.g., real-world) content. The artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of which may be presented in a single channel or in multiple channels (such as stereo video that produces a three-dimensional effect to the viewer). Additionally, in some embodiments, artificial reality may also be associated with applications, products, accessories, services, or some combination thereof, that are used to, for example, create content in an artificial reality and/or are otherwise used in (e.g., perform activities in) an artificial reality. The artificial reality system that provides the artificial reality content may be implemented on various platforms, including an HMD connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.

FIG. 18 is a simplified block diagram of an example of an electronic system 1800 of a near-eye display (e.g., HMD device) for implementing some of the examples disclosed herein. Electronic system 1800 may be used as the electronic system of an HMD device or other near-eye displays described above. In this example, electronic system 1800 may include one or more processor(s) 1810 and a memory 1820. Processor(s) 1810 may be configured to execute instructions for performing operations at a number of components, and can be, for example, a general-purpose processor or microprocessor suitable for implementation within a portable electronic device. Processor(s) 1810 may be communicatively coupled with a plurality of components within electronic system 1800. To realize this communicative coupling, processor(s) 1810 may communicate with the other illustrated components across a bus 1840. Bus 1840 may be any subsystem adapted to transfer data within electronic system 1800. Bus 1840 may include a plurality of computer buses and additional circuitry to transfer data.

Memory 1820 may be coupled to processor(s) 1810. In some embodiments, memory 1820 may offer both short-term and long-term storage and may be divided into several units. Memory 1820 may be volatile, such as static random access memory (SRAM) and/or dynamic random access memory (DRAM) and/or non-volatile, such as read-only memory (ROM), flash memory, and the like. Furthermore, memory 1820 may include removable storage devices, such as secure digital (SD) cards. Memory 1820 may provide storage of computer-readable instructions, data structures, program modules, and other data for electronic system 1800. In some embodiments, memory 1820 may be distributed into different hardware modules. A set of instructions and/or code might be stored on memory 1820. The instructions might take the form of executable code that may be executable by electronic system 1800, and/or might take the form of source and/or installable code, which, upon compilation and/or installation on electronic system 1800 (e.g., using any of a variety of generally available compilers, installation programs, compression/decompression utilities, etc.), may take the form of executable code.

In some embodiments, memory 1820 may store a plurality of application modules 1822 through 1824, which may include any number of applications. Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications. The applications may include a depth sensing function or eye tracking function. Application modules 1822-1824 may include particular instructions to be executed by processor(s) 1810. In some embodiments, certain applications or parts of application modules 1822-1824 may be executable by other hardware modules 1880. In certain embodiments, memory 1820 may additionally include secure memory, which may include additional security controls to prevent copying or other unauthorized access to secure information.

In some embodiments, memory 1820 may include an operating system 1825 loaded therein. Operating system 1825 may be operable to initiate the execution of the instructions provided by application modules 1822-1824 and/or manage other hardware modules 1880 as well as interfaces with a wireless communication subsystem 1830 which may include one or more wireless transceivers. Operating system 1825 may be adapted to perform other operations across the components of electronic system 1800 including threading, resource management, data storage control and other similar functionality.

Wireless communication subsystem 1830 may include, for example, an infrared communication device, a wireless communication device and/or chipset (such as a Bluetooth® device, an IEEE 802.11 device, a Wi-Fi device, a WiMax device, cellular communication facilities, etc.), and/or similar communication interfaces. Electronic system 1800 may include one or more antennas 1834 for wireless communication as part of wireless communication subsystem 1830 or as a separate component coupled to any portion of the system. Depending on desired functionality, wireless communication subsystem 1830 may include separate transceivers to communicate with base transceiver stations and other wireless devices and access points, which may include communicating with different data networks and/or network types, such as wireless wide-area networks (WWANs), wireless local area networks (WLANs), or wireless personal area networks (WPANs). A WWAN may be, for example, a WiMax (IEEE 802.16) network. A WLAN may be, for example, an IEEE 802.11x network. A WPAN may be, for example, a Bluetooth network, an IEEE 802.15x, or some other types of network. The techniques described herein may also be used for any combination of WWAN, WLAN, and/or WPAN. Wireless communications subsystem 1830 may permit data to be exchanged with a network, other computer systems, and/or any other devices described herein. Wireless communication subsystem 1830 may include a means for transmitting or receiving data, such as identifiers of HMD devices, position data, a geographic map, a heat map, photos, or videos, using antenna(s) 1834 and wireless link(s) 1832. Wireless communication subsystem 1830, processor(s) 1810, and memory 1820 may together comprise at least a part of one or more of a means for performing some functions disclosed herein.

Embodiments of electronic system 1800 may also include one or more sensors 1890. Sensor(s) 1890 may include, for example, an image sensor, an accelerometer, a pressure sensor, a temperature sensor, a proximity sensor, a magnetometer, a gyroscope, an inertial sensor (e.g., a module that combines an accelerometer and a gyroscope), an ambient light sensor, or any other similar module operable to provide sensory output and/or receive sensory input, such as a depth sensor or a position sensor. For example, in some implementations, sensor(s) 1890 may include one or more inertial measurement units (IMUs) and/or one or more position sensors. An IMU may generate calibration data indicating an estimated position of the HMD device relative to an initial position of the HMD device, based on measurement signals received from one or more of the position sensors. A position sensor may generate one or more measurement signals in response to motion of the HMD device. Examples of the position sensors may include, but are not limited to, one or more accelerometers, one or more gyroscopes, one or more magnetometers, another suitable type of sensor that detects motion, a type of sensor used for error correction of the IMU, or any combination thereof. The position sensors may be located external to the IMU, internal to the IMU, or any combination thereof. At least some sensors may use a structured light pattern for sensing.

Electronic system 1800 may include a display module 1860. Display module 1860 may be a near-eye display, and may graphically present information, such as images, videos, and various instructions, from electronic system 1800 to a user. Such information may be derived from one or more application modules 1822-1824, virtual reality engine 1826, one or more other hardware modules 1880, a combination thereof, or any other suitable means for resolving graphical content for the user (e.g., by operating system 1825). Display module 1860 may use LCD technology, LED technology (including, for example, OLED, ILED, μ-LED, AMOLED, TOLED, etc.), light emitting polymer display (LPD) technology, or some other display technology.

Electronic system 1800 may include a user input/output module 1870. User input/output module 1870 may allow a user to send action requests to electronic system 1800. An action request may be a request to perform a particular action. For example, an action request may be to start or end an application or to perform a particular action within the application. User input/output module 1870 may include one or more input devices. Example input devices may include a touchscreen, a touch pad, microphone(s), button(s), dial(s), switch(es), a keyboard, a mouse, a game controller, or any other suitable device for receiving action requests and communicating the received action requests to electronic system 1800. In some embodiments, user input/output module 1870 may provide haptic feedback to the user in accordance with instructions received from electronic system 1800. For example, the haptic feedback may be provided when an action request is received or has been performed.

Electronic system 1800 may include a camera 1850 that may be used to take photos or videos of a user, for example, for tracking the user's eye position. Camera 1850 may also be used to take photos or videos of the environment, for example, for VR, AR, or MR applications. Camera 1850 may include, for example, a complementary metal-oxide- semiconductor (CMOS) image sensor with a few millions or tens of millions of pixels. In some implementations, camera 1850 may include two or more cameras that may be used to capture 3-D images.

In some embodiments, electronic system 1800 may include a plurality of other hardware modules 1880. Each of other hardware modules 1880 may be a physical module within electronic system 1800. While each of other hardware modules 1880 may be permanently configured as a structure, some of other hardware modules 1880 may be temporarily configured to perform specific functions or temporarily activated. Examples of other hardware modules 1880 may include, for example, an audio output and/or input module (e.g., a microphone or speaker), a near field communication (NFC) module, a rechargeable battery, a battery management system, a wired/wireless battery charging system, etc. In some embodiments, one or more functions of other hardware modules 1880 may be implemented in software.

In some embodiments, memory 1820 of electronic system 1800 may also store a virtual reality engine 1826. Virtual reality engine 1826 may execute applications within electronic system 1800 and receive position information, acceleration information, velocity information, predicted future positions, or any combination thereof of the HMD device from the various sensors. In some embodiments, the information received by virtual reality engine 1826 may be used for producing a signal (e.g., display instructions) to display module 1860. For example, if the received information indicates that the user has looked to the left, virtual reality engine 1826 may generate content for the HMD device that mirrors the user's movement in a virtual environment. Additionally, virtual reality engine 1826 may perform an action within an application in response to an action request received from user input/output module 1870 and provide feedback to the user. The provided feedback may be visual, audible, or haptic feedback. In some implementations, processor(s) 1810 may include one or more GPUs that may execute virtual reality engine 1826.

In various implementations, the above-described hardware and modules may be implemented on a single device or on multiple devices that can communicate with one another using wired or wireless connections. For example, in some implementations, some components or modules, such as GPUs, virtual reality engine 1826, and applications (e.g., tracking application), may be implemented on a console separate from the head-mounted display device. In some implementations, one console may be connected to or support more than one HMD.

In alternative configurations, different and/or additional components may be included in electronic system 1800. Similarly, functionality of one or more of the components can be distributed among the components in a manner different from the manner described above. For example, in some embodiments, electronic system 1800 may be modified to include other system environments, such as an AR system environment and/or an MR environment.

The methods, systems, and devices discussed above are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, in alternative configurations, the methods described may be performed in an order different from that described, and/or various stages may be added, omitted, and/or combined. Also, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Also, technology evolves and, thus, many of the elements are examples that do not limit the scope of the disclosure to those specific examples.

Specific details are given in the description to provide a thorough understanding of the embodiments. However, embodiments may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. This description provides example embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the preceding description of the embodiments will provide those skilled in the art with an enabling description for implementing various embodiments. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the present disclosure.

Also, some embodiments were described as processes depicted as flow diagrams or block diagrams. Although each may describe the operations as a sequential process, many of the operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional steps not included in the figure. Furthermore, embodiments of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the associated tasks may be stored in a computer-readable medium such as a storage medium. Processors may perform the associated tasks.

It will be apparent to those skilled in the art that substantial variations may be made in accordance with specific requirements. For example, customized or special-purpose hardware might also be used, and/or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both. Further, connection to other computing devices such as network input/output devices may be employed.

With reference to the appended figures, components that can include memory can include non-transitory machine-readable media. The term “machine-readable medium” and “computer-readable medium” may refer to any storage medium that participates in providing data that causes a machine to operate in a specific fashion. In embodiments provided hereinabove, various machine-readable media might be involved in providing instructions/code to processing units and/or other device(s) for execution. Additionally or alternatively, the machine-readable media might be used to store and/or carry such instructions/code. In many implementations, a computer-readable medium is a physical and/or tangible storage medium. Such a medium may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and/or optical media such as compact disk (CD) or digital versatile disk (DVD), punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and/or code. A computer program product may include code and/or machine-executable instructions that may represent a procedure, a function, a subprogram, a program, a routine, an application (App), a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements.

Those of skill in the art will appreciate that information and signals used to communicate the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Terms, “and” and “or” as used herein, may include a variety of meanings that are also expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of” if used to associate a list, such as A, B, or C, can be interpreted to mean A, B, C, or any combination of A, B, and/or C, such as AB, AC, BC, AA, ABC, AAB, AABBCCC, or the like.

Further, while certain embodiments have been described using a particular combination of hardware and software, it should be recognized that other combinations of hardware and software are also possible. Certain embodiments may be implemented only in hardware, or only in software, or using combinations thereof. In one example, software may be implemented with a computer program product containing computer program code or instructions executable by one or more processors for performing any or all of the steps, operations, or processes described in this disclosure, where the computer program may be stored on a non-transitory computer readable medium. The various processes described herein can be implemented on the same processor or different processors in any combination.

Where devices, systems, components or modules are described as being configured to perform certain operations or functions, such configuration can be accomplished, for example, by designing electronic circuits to perform the operation, by programming programmable electronic circuits (such as microprocessors) to perform the operation such as by executing computer instructions or code, or processors or cores programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof. Processes can communicate using a variety of techniques, including, but not limited to, conventional techniques for inter-process communications, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, subtractions, deletions, and other modifications and changes may be made thereunto without departing from the broader spirit and scope as set forth in the claims. Thus, although specific embodiments have been described, these are not intended to be limiting. Various modifications and equivalents are within the scope of the following claims.