Meta Patent | Cu pads for reduced dishing in low temperature annealing and bonding

where η_EQE is the external quantum efficiency of image source 412, η_in is the in-coupling efficiency of light from image source 412 into the waveguide (e.g., substrate 420), and η_out is the outcoupling efficiency of light from the waveguide towards the user's eye by output coupler 440. Thus, the overall efficiency η_tot of the waveguide-based display can be improved by improving one or more of η_EQE, η_in, and η_out.

The optical coupler (e.g., input coupler 430 or coupler 532) that couples the emitted light from a light source to a waveguide may include, for example, a grating, a lens, a micro-lens, a prism. In some embodiments, light from a small light source (e.g., a micro-LED) can be directly (e.g., end-to-end) coupled from the light source to a waveguide, without using an optical coupler. In some embodiments, the optical coupler (e.g., a lens or a parabolic-shaped reflector) may be manufactured on the light source.

The light sources, image sources, or other displays described above may include one or more LEDs. For example, each pixel in a display may include three subpixels that include a red micro-LED, a green micro-LED, and a blue micro-LED. A semiconductor light emitting diode generally includes an active light emitting layer within multiple layers of semiconductor materials. The multiple layers of semiconductor materials may include different compound materials or a same base material with different dopants and/or different doping densities. For example, the multiple layers of semiconductor materials may generally include an n-type material layer, an active layer that may include hetero-structures (e.g., one or more quantum wells), and a p-type material layer. The multiple layers of semiconductor materials may be grown on a surface of a substrate having a certain orientation.

Photons can be generated in a semiconductor LED (e.g., a micro-LED) at a certain internal quantum efficiency through the recombination of electrons and holes within the active layer (e.g., including one or more semiconductor layers). The generated light may then be extracted from the LEDs in a particular direction or within a particular solid angle. The ratio between the number of emitted photons extracted from the LED and the number of electrons passing through the LED is referred to as the external quantum efficiency, which describes how efficiently the LED converts injected electrons to photons that are extracted from the device. The external quantum efficiency may be proportional to the injection efficiency, the internal quantum efficiency, and the extraction efficiency. The injection efficiency refers to the proportion of electrons passing through the device that are injected into the active region. The extraction efficiency is the proportion of photons generated in the active region that escape from the device. For LEDs, and in particular, micro-LEDs with reduced physical dimensions, improving the internal and external quantum efficiency can be challenging. In some embodiments, to increase the light extraction efficiency, a mesa that includes at least some of the layers of semiconductor materials may be formed.

FIG. 7A illustrates an example of an LED 700 having a vertical mesa structure. LED 700 may be a light emitter in light source 510, 540, or 642. LED 700 may be a micro-LED made of inorganic materials, such as multiple layers of semiconductor materials. The layered semiconductor light emitting device may include multiple layers of III-V semiconductor materials. A III-V semiconductor material may include one or more Group III elements, such as aluminum (Al), gallium (Ga), or indium (In), in combination with a Group V element, such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). When the Group V element of the III-V semiconductor material includes nitrogen, the III-V semiconductor material is referred to as a III-nitride material. The layered semiconductor light emitting device may be manufactured by growing multiple epitaxial layers on a substrate using techniques such as vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular beam epitaxy (MBE), or metalorganic chemical vapor deposition (MOCVD). For example, the layers of the semiconductor materials may be grown layer-by-layer on a substrate with a certain crystal lattice orientation (e.g., polar, nonpolar, or semi-polar orientation), such as a GaN, GaAs, or GaP substrate, or a substrate including, but not limited to, sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinels, or quaternary tetragonal oxides sharing the beta-LiAlO₂ structure, where the substrate may be cut in a specific direction to expose a specific plane as the growth surface.

In the example shown in FIG. 7A, LED 700 may include a substrate 710, which may include, for example, a sapphire substrate or a GaN substrate. A semiconductor layer 720 may be grown on substrate 710. Semiconductor layer 720 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One or more active layers 730 may be grown on semiconductor layer 720 to form an active region. Active layer 730 may include III-V materials, such as one or more InGaN layers, one or more AlGaInP layers, and/or one or more GaN layers, which may form one or more heterostructures, such as one or more quantum wells or MQWs. A semiconductor layer 740 may be grown on active layer 730. Semiconductor layer 740 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One of semiconductor layer 720 and semiconductor layer 740 may be a p-type layer and the other one may be an n-type layer. Semiconductor layer 720 and semiconductor layer 740 sandwich active layer 730 to form the light emitting region. For example, LED 700 may include a layer of InGaN situated between a layer of p-type GaN doped with magnesium and a layer of n-type GaN doped with silicon or oxygen. In some embodiments, LED 700 may include a layer of AlGaInP situated between a layer of p-type AlGaInP doped with zinc or magnesium and a layer of n-type AlGaInP doped with selenium, silicon, or tellurium.

In some embodiments, an electron-blocking layer (EBL) (not shown in FIG. 7A) may be grown to form a layer between active layer 730 and at least one of semiconductor layer 720 or semiconductor layer 740. The EBL may reduce the electron leakage current and improve the efficiency of the LED. In some embodiments, a heavily-doped semiconductor layer 750, such as a P⁺ or P⁺⁺ semiconductor layer, may be formed on semiconductor layer 740 and act as a contact layer for forming an ohmic contact and reducing the contact impedance of the device. In some embodiments, a conductive layer 760 may be formed on heavily-doped semiconductor layer 750. Conductive layer 760 may include, for example, an indium tin oxide (ITO) or Al/Ni/Au film. In one example, conductive layer 760 may include a transparent ITO layer.

To make contact with semiconductor layer 720 (e.g., an n-GaN layer) and to more efficiently extract light emitted by active layer 730 from LED 700, the semiconductor material layers (including heavily-doped semiconductor layer 750, semiconductor layer 740, active layer 730, and semiconductor layer 720) may be etched to expose semiconductor layer 720 and to form a mesa structure that includes layers 720-760. The mesa structure may confine the carriers within the device. Etching the mesa structure may lead to the formation of mesa sidewalls 732 that may be orthogonal to the growth planes. A passivation layer 770 may be formed on mesa sidewalls 732 of the mesa structure. Passivation layer 770 may include an oxide layer, such as a SiO₂ layer, and may act as a reflector to reflect emitted light out of LED 700. A contact layer 780, which may include a metal layer, such as Al, Au, Ni, Ti, or any combination thereof, may be formed on semiconductor layer 720 and may act as an electrode of LED 700. In addition, another contact layer 790, such as an Al/Ni/Au metal layer, may be formed on conductive layer 760 and may act as another electrode of LED 700.

When a voltage signal is applied to contact layers 780 and 790, electrons and holes may recombine in active layer 730, where the recombination of electrons and holes may cause photon emission. The wavelength and energy of the emitted photons may depend on the energy bandgap between the valence band and the conduction band in active layer 730. For example, InGaN active layers may emit green or blue light, AlGaN active layers may emit blue to ultraviolet light, while AlGaInP active layers may emit red, orange, yellow, or green light. The emitted photons may be reflected by passivation layer 770 and may exit LED 700 from the top (e.g., conductive layer 760 and contact layer 790) or bottom (e.g., substrate 710).

In some embodiments, LED 700 may include one or more other components, such as a lens, on the light emission surface, such as substrate 710, to focus or collimate the emitted light or couple the emitted light into a waveguide. In some embodiments, an LED may include a mesa of another shape, such as planar, conical, semi-parabolic, or parabolic, and a base area of the mesa may be circular, rectangular, hexagonal, or triangular. For example, the LED may include a mesa of a curved shape (e.g., paraboloid shape) and/or a non-curved shape (e.g., conic shape). The mesa may be truncated or non-truncated.

FIG. 7B is a cross-sectional view of an example of an LED 705 having a parabolic mesa structure. Similar to LED 700, LED 705 may include multiple layers of semiconductor materials, such as multiple layers of III-V semiconductor materials. The semiconductor material layers may be epitaxially grown on a substrate 715, such as a GaN substrate or a sapphire substrate. For example, a semiconductor layer 725 may be grown on substrate 715.

Semiconductor layer 725 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One or more active layer 735 may be grown on semiconductor layer 725. Active layer 735 may include III-V materials, such as one or more InGaN layers, one or more AlGaInP layers, and/or one or more GaN layers, which may form one or more heterostructures, such as one or more quantum wells. A semiconductor layer 745 may be grown on active layer 735. Semiconductor layer 745 may include a III-V material, such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One of semiconductor layer 725 and semiconductor layer 745 may be a p-type layer and the other one may be an n-type layer.

To make contact with semiconductor layer 725 (e.g., an n-type GaN layer) and to more efficiently extract light emitted by active layer 735 from LED 705, the semiconductor layers may be etched to expose semiconductor layer 725 and to form a mesa structure that includes layers 725-745. The mesa structure may confine carriers within the injection area of the device. Etching the mesa structure may lead to the formation of mesa side walls (also referred to herein as facets) that may be non-parallel with, or in some cases, orthogonal, to the growth planes associated with crystalline growth of layers 725-745.

As shown in FIG. 7B, LED 705 may have a mesa structure that includes a flat top. A dielectric layer 775 (e.g., SiO₂ or SiN) may be formed on the facets of the mesa structure. In some embodiments, dielectric layer 775 may include multiple layers of dielectric materials. In some embodiments, a metal layer 795 may be formed on dielectric layer 775. Metal layer 795 may include one or more metal or metal alloy materials, such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), copper (Cu), or any combination thereof. Dielectric layer 775 and metal layer 795 may form a mesa reflector that can reflect light emitted by active layer 735 toward substrate 715. In some embodiments, the mesa reflector may be parabolic-shaped to act as a parabolic reflector that may at least partially collimate the emitted light.

Electrical contact 765 and electrical contact 785 may be formed on semiconductor layer 745 and semiconductor layer 725, respectively, to act as electrodes. Electrical contact 765 and electrical contact 785 may each include a conductive material, such as Al, Au, Pt, Ag, Ni, Ti, Cu, or any combination thereof (e.g., Ag/Pt/Au or Al/Ni/Au), and may act as the electrodes of LED 705. In the example shown in FIG. 7B, electrical contact 785 may be an n-contact, and electrical contact 765 may be a p-contact. Electrical contact 765 and semiconductor layer 745 (e.g., a p-type semiconductor layer) may form a back reflector for reflecting light emitted by active layer 735 back toward substrate 715. In some embodiments, electrical contact 765 and metal layer 795 include same material(s) and can be formed using the same processes. In some embodiments, an additional conductive layer (not shown) may be included as an intermediate conductive layer between the electrical contacts 765 and 785 and the semiconductor layers.

When a voltage signal is applied across electrical contacts 765 and 785, electrons and holes may recombine in active layer 735. The recombination of electrons and holes may cause photon emission, thus producing light. The wavelength and energy of the emitted photons may depend on the energy bandgap between the valence band and the conduction band in active layer 735. For example, InGaN active layers may emit green or blue light, while AlGaInP active layers may emit red, orange, yellow, or green light. The emitted photons may propagate in many different directions, and may be reflected by the mesa reflector and/or the back reflector and may exit LED 705, for example, from the bottom side (e.g., substrate 715) shown in FIG. 7B. One or more other secondary optical components, such as a lens or a grating, may be formed on the light emission surface, such as substrate 715, to focus or collimate the emitted light and/or couple the emitted light into a waveguide.

When the mesa structure is formed (e.g., etched), the facets of the mesa structure, such as mesa sidewalls 732, may include some imperfections, such as unsatisfied bonds, chemical contamination, and structural damages (e.g., when dry-etched), that may decrease the internal quantum efficiency of the LED. For example, at the facets, the atomic lattice structure of the semiconductor layers may come to an abrupt end, where some atoms of the semiconductor materials may lack neighbors to which bonds may be attached. This results in “dangling bonds,” which may be characterized by unpaired valence electrons. These dangling bonds create energy levels that otherwise would not exist within the bandgap of the semiconductor material, causing non-radiative electron-hole recombination at or near the facets of the mesa structure. Thus, these imperfections may become the recombination centers where electrons and holes may be confined until they combine non-radiatively.

FIG. 8A illustrates an example of a method of die-to-wafer bonding for arrays of LEDs according to certain embodiments. In the example shown in FIG. 8A, an LED array 801 may include a plurality of LEDs 807 (including a bonding layer formed thereon) on a carrier substrate 805. Carrier substrate 805 may include various materials, such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. LEDs 807 may be fabricated by, for example, growing various epitaxial layers, forming mesa structures, and forming electrical contacts or electrodes, before performing the bonding. The epitaxial layers may include various materials, such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP, (AlGaIn)AsN, (Eu:InGa)N, (AlGaIn)N, or the like, and may include an n-type layer, a p-type layer, and an active layer that includes one or more heterostructures, such as one or more quantum wells or MQWs. The electrical contacts may include various conductive materials, such as a metal or a metal alloy.

A wafer 803 may include a base layer 809 having passive or active integrated circuits (e.g., driver circuits 811) fabricated thereon. Base layer 809 may include, for example, a silicon wafer. Driver circuits 811 may be used to control the operations of LEDs 807. For example, the driver circuit for each LED 807 may include a 2T1C pixel structure that has two transistors and one capacitor. Wafer 803 may also include a bonding layer 813. Bonding layer 813 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, and the like. In some embodiments, a patterned layer 815 may be formed on a surface of bonding layer 813, where patterned layer 815 may include a metallic grid made of a conductive material, such as Cu, Ag, Au, Al, or the like.

LED array 801 may be bonded to wafer 803 via bonding layer 813 or patterned layer 815. For example, patterned layer 815 may include metal pads or bumps made of various materials, such as CuSn, AuSn, or nanoporous Au, that may be used to align LEDs 807 of LED array 801 with corresponding driver circuits 811 on wafer 803. In one example, LED array 801 may be brought toward wafer 803 until LEDs 807 come into contact with respective metal pads or bumps corresponding to driver circuits 811. Some or all of LEDs 807 may be aligned with driver circuits 811, and may then be bonded to wafer 803 via patterned layer 815 by various bonding techniques, such as metal-to-metal bonding. After LEDs 807 have been bonded to wafer 803, carrier substrate 805 may be removed from LEDs 807.

FIG. 8B illustrates an example of a method of wafer-to-wafer bonding for arrays of LEDs according to certain embodiments. As shown in FIG. 8B, a first wafer 802 may include a substrate 804, a first semiconductor layer 806, active layers 808, and a second semiconductor layer 810. Substrate 804 may include various materials, such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. First semiconductor layer 806, active layers 808, and second semiconductor layer 810 may include various semiconductor materials, such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP, (AlGaIn)AsN, (AlGaIn)Pas, (Eu:InGa)N, (AlGaIn)N, or the like. In some embodiments, first semiconductor layer 806 may be an n-type layer, and second semiconductor layer 810 may be a p-type layer. For example, first semiconductor layer 806 may be an n-doped GaN layer (e.g., doped with Si or Ge), and second semiconductor layer 810 may be a p-doped GaN layer (e.g., doped with Mg, Ca, Zn, or Be). Active layers 808 may include, for example, one or more GaN layers, one or more InGaN layers, one or more AlInGaP layers, and the like, which may form one or more heterostructures, such as one or more quantum wells or MQWs.

In some embodiments, first wafer 802 may also include a bonding layer. Bonding layer 812 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, or the like. In one example, bonding layer 812 may include p-contacts and/or n-contacts (not shown). In some embodiments, other layers may also be included on first wafer 802, such as a buffer layer between substrate 804 and first semiconductor layer 806. The buffer layer may include various materials, such as polycrystalline GaN or MN. In some embodiments, a contact layer may be between second semiconductor layer 810 and bonding layer 812. The contact layer may include any suitable material for providing an electrical contact to second semiconductor layer 810 and/or first semiconductor layer 806.

First wafer 802 may be bonded to wafer 803 that includes driver circuits 811 and bonding layer 813 as described above, via bonding layer 813 and/or bonding layer 812. Bonding layer 812 and bonding layer 813 may be made of the same material or different materials. Bonding layer 813 and bonding layer 812 may be substantially flat. First wafer 802 may be bonded to wafer 803 by various methods, such as metal-to-metal bonding, eutectic bonding, metal oxide bonding, anodic bonding, thermo-compression bonding, ultraviolet (UV) bonding, and/or fusion bonding.

As shown in FIG. 8B, first wafer 802 may be bonded to wafer 803 with the p-side (e.g., second semiconductor layer 810) of first wafer 802 facing down (i.e., toward wafer 803). After bonding, substrate 804 may be removed from first wafer 802, and first wafer 802 may then be processed from the n-side. The processing may include, for example, the formation of certain mesa shapes for individual LEDs, as well as the formation of optical components corresponding to the individual LEDs.

FIGS. 9A-9D illustrate an example of a method of hybrid bonding for arrays of LEDs according to certain embodiments. The hybrid bonding may generally include wafer cleaning and activation, high-precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials at the surfaces of the wafers at room temperature, and metal bonding of the contacts by annealing at elevated temperatures. FIG. 9A shows a substrate 910 with passive or active circuits 920 manufactured thereon. As described above with respect to FIGS. 8A-8B, substrate 910 may include, for example, a silicon wafer. Circuits 920 may include driver circuits for the arrays of LEDs. A bonding layer may include dielectric regions 940 and contact pads 930 connected to circuits 920 through electrical interconnects 922. Contact pads 930 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like. Dielectric materials in dielectric regions 940 may include SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, where the planarization or polishing may cause dishing (a bowl like profile) in the contact pads. The surfaces of the bonding layers may be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., Ar) beam 905. The activated surface may be atomically clean and may be reactive for formation of direct bonds between wafers when they are brought into contact, for example, at room temperature.

FIG. 9B illustrates a wafer 950 including an array of micro-LEDs 970 fabricated thereon as described above. Wafer 950 may be a carrier wafer (or a growth substrate) and may include, for example, GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. Micro-LEDs 970 may include an n-type layer, an active region, and a p-type layer epitaxially grown on wafer 950. The epitaxial layers may include various III-V semiconductor materials described above, and may be processed from the p-type layer side to etch mesa structures in the epitaxial layers, such as substantially vertical structures, parabolic structures, conic structures, or the like. Passivation layers and/or reflection layers may be formed on the sidewalls of the mesa structures. P-contacts 980 and n-contacts 982 may be formed in a dielectric material layer 960 deposited on the mesa structures and may make electrical contacts with the p-type layer and the n-type layers, respectively. Dielectric materials in dielectric material layer 960 may include, for example, SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like. P-contacts 980 and n-contacts 982 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like. The top surfaces of p-contacts 980, n-contacts 982, and dielectric material layer 960 may form a bonding layer. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, where the polishing may cause dishing in p-contacts 980 and n-contacts 982. The bonding layer may then be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., Ar) beam 915. The activated surface may be atomically clean and reactive for formation of direct bonds between wafers when they are brought into contact, for example, at room temperature.

FIG. 9C illustrates a room temperature bonding process for bonding the dielectric materials in the bonding layers. For example, after the bonding layer that includes dielectric regions 940 and contact pads 930 and the bonding layer that includes p-contacts 980, n-contacts 982, and dielectric material layer 960 are surface activated, wafer 950 and micro-LEDs 970 may be turned upside down and brought into contact with substrate 910 and the circuits formed thereon. In some embodiments, compression pressure 925 may be applied to substrate 910 and wafer 950 such that the bonding layers are pressed against each other. Due to the surface activation and the dishing in the contacts, dielectric regions 940 and dielectric material layer 960 may be in direct contact, and may react and form chemical bonds between them because the surface atoms may have dangling bonds and may be in unstable energy states after the activation. Thus, the dielectric materials in dielectric regions 940 and dielectric material layer 960 may be bonded together with or without heat treatment or pressure.

FIG. 9D illustrates an annealing process for bonding the contacts in the bonding layers after bonding the dielectric materials in the bonding layers. For example, contact pads 930 and p-contacts 980 or n-contacts 982 may be bonded together by annealing at, for example, about 90-400° C. or higher. During the annealing process, heat 935 may cause the contacts to expand more than the dielectric materials (due to different coefficients of thermal expansion), and thus may close the dishing gaps between the contacts such that contact pads 930 and p-contacts 980 or n-contacts 982 may be in contact and may form direct metallic bonds at the activated surfaces.

In some embodiments where the two bonded wafers include materials having different coefficients of thermal expansion (CTEs), the dielectric materials bonded at room temperature may help to reduce or prevent misalignment of the contact pads caused by the different thermal expansions. In some embodiments, to further reduce or avoid the misalignment of the contact pads at a high temperature during annealing, trenches may be formed between micro-LEDs, between groups of micro-LEDs, through part or all of the substrate, or the like, before bonding.

After the micro-LEDs are bonded to the driver circuits, the substrate on which the micro-LEDs are fabricated may be thinned or removed, and various secondary optical components may be fabricated on the light emitting surfaces of the micro-LEDs to, for example, extract, collimate, and redirect the light emitted from the active regions of the micro-LEDs. In one example, micro-lenses may be formed on the micro-LEDs, where each micro-lens may correspond to a respective micro-LED and may help to improve the light extraction efficiency and collimate the light emitted by the micro-LED. In some embodiments, the secondary optical components may be fabricated in the substrate or the n-type layer of the micro-LEDs. In some embodiments, the secondary optical components may be fabricated in a dielectric layer deposited on the n-type side of the micro-LEDs. Examples of the secondary optical components may include a lens, a grating, an antireflection (AR) coating, a prism, a photonic crystal, or the like.

FIG. 10 illustrates an example of an LED array 1000 with secondary optical components fabricated thereon according to certain embodiments. LED array 1000 may be made by bonding an LED chip or wafer with a silicon wafer including electrical circuits fabricated thereon, using any suitable bonding techniques described above with respect to, for example, FIGS. 8A-9D. In the example shown in FIG. 10, LED array 1000 may be bonded using a wafer-to-wafer hybrid bonding technique as described above with respect to FIG. 9A-9D. LED array 1000 may include a substrate 1010, which may be, for example, a silicon wafer. Integrated circuits 1020, such as LED driver circuits, may be fabricated on substrate 1010. Integrated circuits 1020 may be connected to p-contacts 1074 and n-contacts 1072 of micro-LEDs 1070 through interconnects 1022 and contact pads 1030, where contact pads 1030 may form metallic bonds with p-contacts 1074 and n-contacts 1072. Dielectric layer 1040 on substrate 1010 may be bonded to dielectric layer 1060 through fusion bonding.

The substrate (not shown) of the LED chip or wafer may be thinned or may be removed to expose the n-type layer 1050 of micro-LEDs 1070. Various secondary optical components, such as a spherical micro-lens 1082, a grating 1084, a micro-lens 1086, an antireflection layer 1088, and the like, may be formed in or on top of n-type layer 1050. For example, spherical micro-lens arrays may be etched in the semiconductor materials of micro-LEDs 1070 using a gray-scale mask and a photoresist with a linear response to exposure light, or using an etch mask formed by thermal reflowing of a patterned photoresist layer. The secondary optical components may also be etched in a dielectric layer deposited on n-type layer 1050 using similar photolithographic techniques or other techniques. For example, micro-lens arrays may be formed in a polymer layer through thermal reflowing of the polymer layer that is patterned using a binary mask. The micro-lens arrays in the polymer layer may be used as the secondary optical components or may be used as the etch mask for transferring the profiles of the micro-lens arrays into a dielectric layer or a semiconductor layer. The dielectric layer may include, for example, SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like. In some embodiments, a micro-LED 1070 may have multiple corresponding secondary optical components, such as a micro-lens and an anti-reflection coating, a micro-lens etched in the semiconductor material and a micro-lens etched in a dielectric material layer, a micro-lens and a grating, a spherical lens and an aspherical lens, and the like. Three different secondary optical components are illustrated in FIG. 10 to show some examples of secondary optical components that can be formed on micro-LEDs 1070, which does not necessary imply that different secondary optical components are used simultaneously for every LED array.

In the processes described above with respect to, for example, FIGS. 9A-9D, it can be very challenging to precisely align the bonding pads on the micro-LED devices with the bonding pads on the drive circuits, and form reliable bonding at the interfaces that may include both dielectric materials (e.g., SiO₂) and metal (e.g., Cu) bonding pads. For example, when the pitch of the micro-LED device is about 2 or 3 μm or lower, the bonding pads may have a linear dimension less than about 1 μm (e.g., about 0.7 μm), in order to avoid shorting between adjacent micro-LEDs. On the other hand, for small bonding pads, misalignment may reduce the metal-to-metal overlap between the bonding pads, increase the contact resistance (or may even be an open circuit), and/or cause diffusion of metals into the dielectric material and thus may cause current leakage.

FIG. 11A illustrates an example of hybrid bonding between two wafers or dice. FIG. 11A shows the bonding layers of two wafers or dice, where a first wafer (e.g., a GaAs or sapphire wafer with micro-LEDs fabricated thereon) may include a bonding layer 1110, and a second wafer (e.g., a silicon wafer with drive circuits fabricated thereon) may include a bonding layer 1150. Bonding layer 1110 may include an oxide layer 1120 (e.g., a SiO₂ layer) with bonding pads 1140 (or metal plugs) formed in oxide layer 1120. Bonding layer 1110 may be formed by, for example, depositing oxide layer 1120 on the first wafer, planarizing oxide layer 1120, selectively etching oxide layer 1120 to form trenches in oxide layer 1120, depositing a barrier layer 1130 (e.g., Ti or W) on sidewalls of the trenches, depositing a metal layer (e.g., Cu, Au, or Al) to fill the trenches, removing the metal layer on top of oxide layer 1120, and planarizing the surface of bonding layer 1110 (e.g., using chemical mechanical planarization). Barrier layer 1130 may be used to reduce or prevent the diffusion of the metal material to other regions that may cause leakage. The metal layer remains in the trenches may form bonding pads 1140. Similarly, bonding layer 1150 may be formed by, for example, depositing oxide layer 1160 on the second wafer, planarizing oxide layer 1160, selectively etching oxide layer 1160 to form trenches in oxide layer 1160, depositing a barrier layer 1170 (e.g., Ti or W) on sidewalls of the trenches, depositing a metal (e.g., Cu, Au, or Al) layer to fill the trenches, removing the metal layer on top of oxide layer 1160, and planarizing the surface of bonding layer 1150 (e.g., using chemical mechanical planarization). The metal layer remaining in the trenches may form bonding pads 1180.

As described above, the bonding surfaces of bonding layers 1110 and 1150 may be conditioned before hybrid bonding. For example, the surfaces of the metal bonding pads (e.g., Cu, Au, or Al pads) may include a surface oxide and/or other contamination. Excessive oxidation and/or contamination of the bonding surfaces may drastically decrease the bonding strength and electrical conductivity. Diffusion bonding may be performed in a vacuum or in an inert atmosphere (e.g., dry nitrogen, argon, or helium) to reduce detrimental oxidation or contamination of the bonding surfaces. The bonding layer may be cleaned and activated by, for example, an ion (e.g., plasma) beam or a fast atom (e.g., Ar) beam. Ar sputtering may remove the Cu oxide layer. The activated surface may be atomically clean and reactive for formation of direct bonds between wafers when they are brought into contact, for example, at room temperature. Surface treatments prior to plasma may include processes for removing surface oxide layers on the metal using citric acid, oxalic acid, and the like.

During the hybrid bonding, bonding layers 1110 and 1150 may be brought into contact. In some embodiments, compressive force may be applied to bonding layers 1110 and 1150 such that bonding layers 1110 and 1150 are pressed against each other. Due to the surface activation and the dishing in the bonding pads 1140 and 1180, the oxide of oxide layer 1120 and the oxide of oxide layer 1160 may be in direct contact, and may react and form chemical bonds between them because the surface atoms may have dangling bonds and may be in unstable energy states after the activation. Thus, the oxide of oxide layer 1120 and the oxide of oxide layer 1160 may be bonded together by van der Waals attractions, with or without heat treatment or pressure. During annealing, oxide layer 1120 that is in contact with oxide layer 1160 may strengthen the bonds through a two-step condensation reaction to fuse the oxide-oxide interface together. The bonded wafer stack may be further annealed to cause the metal contacts to expand such that bonding pads 1140 and 1180 may be in contact and may form direct metallic bonds at the activated surfaces.

FIG. 11B illustrates an example of misalignment during the hybrid bonding of two wafers or dice. For micro-LED devices with small pitches (e.g., less than about 5 μm, 3 μm, or 2 μm), in order to have sufficiently large areas for strong dielectric bonding of the oxide-oxide interfaces at room temperature, the metal bonding pads may need to be small, such as about one quarter, one third, or one half of the total bond interface area. Precise alignment of the metal bonding pads may be needed to make good electrical connections between bonding pads 1140 and 1180. In the example illustrated in FIG. 11B, bonding pads 1140 and 1180 may be misaligned, and the contact region between bonding pads 1140 and 1180 may be smaller than the bonding area of a bonding pad 1140 or a bonding pad 1180. In addition, due to the misalignment, the metal material of bonding pads 1140 and 1180 may be in direct contact with the oxide material of the bonding layers, and thus may diffuse into the oxide material and may cause leakage current between bonding pads of adjacent micro-LEDs.

FIG. 11C illustrates an example of a die stack formed by hybrid bonding of a first wafer 1102 and second wafer 1104. The illustrated example shows misalignment of the bonding pads at a bonding interface 1106. The misalignment may increase the resistance at the bonding interface and may cause diffusion of the metal material (e.g., Cu) into the oxide material as described above. In some cases, the bonding pads are small and the misalignment may be large at least in some regions. Thus, some bonding pads on a wafer may not be in contact with corresponding bonding pads on the other wafer, and therefore some micro-LED electrodes may not be connected to the drive circuits.

FIGS. 12A-12C illustrate examples of bonding pad designs that may mitigate misalignment during hybrid bonding to a certain degree. However, these bonding pad designs may reduce the dielectric bonding regions at the bonding surfaces or may cause short between bonding pads of adjacent micro-LEDs. In the example shown in FIG. 12A, a first wafer (e.g., GaAs wafer with micro-LEDs fabricated thereon) may including a bonding layer 1212, and a second wafer (e.g., a silicon wafer with drive circuits fabricated thereon) may include a bonding layer 1242. Bonding layer 1212 may include an oxide (e.g., SiO₂) layer 1222 with bonding pads 1232 (or metal plugs) formed in oxide layer 1222 as described above. One or more sidewall layers (e.g., an adhesion layer, a barrier layer, and a seed layer, not shown in FIG. 12A) may be between oxide layer 1222 and bonding pads 1232. Bonding layer 1242 may include an oxide (e.g., SiO₂) layer 1252 with bonding pads 1262 (or metal plugs) formed in oxide layer 1252 as described above. One or more sidewall layers (not shown in FIG. 12A) may be between oxide layer 1252 and bonding pads 1262. Bonding pads 1262 may be larger than bonding pads 1232 such that bonding pads 1232 may be in full contact with bonding pads 1262 even if there is some misalignment.

In the example shown in FIG. 12B, a first wafer (e.g., GaAs wafer with micro-LEDs fabricated thereon) may including a bonding layer 1214, and a second wafer (e.g., a silicon wafer with drive circuits fabricated thereon) may include a bonding layer 1244. Bonding layer 1214 may include an oxide (e.g., SiO₂) layer 1224 with metal bonding pads 1234 (or metal plugs) formed in oxide layer 1224 as described above. One or more sidewall layers (not shown in FIG. 12B) may be between oxide layer 1224 and bonding pads 1234. Bonding layer 1244 may include an oxide (e.g., SiO₂) layer 1254 with bonding pads 1264 (or metal plugs) formed in oxide layer 1254 as described above. One or more sidewall layers (not shown in FIG. 12B) may be between oxide layer 1254 and bonding pads 1264. Bonding pads 1264 may include two sections that have different sizes, where a top portion 1270 at the bonding surface may be larger than the other portion of bonding pads 1264 and larger than bonding pads 1234, such that bonding pads 1234 may be in full contact with bonding pads 1264 even if there is some misalignment.

In the example shown in FIG. 12C, a first wafer (e.g., GaAs wafer with micro-LEDs fabricated thereon) may including a bonding layer 1216, and a second wafer (e.g., a silicon wafer with drive circuits fabricated thereon) may include a bonding layer 1246. Bonding layer 1216 may include an oxide (e.g., SiO₂) layer 1226 with bonding pads 1236 (or metal plugs) formed in oxide layer 1226 as described above. Bonding pads 1236 may include two or more sections that have different sizes, where a top portion 1274 at the bonding surface may be larger than other portions of bonding pads 1236. One or more sidewall layers (not shown in FIG. 12C) may be between oxide layer 1226 and bonding pads 1236. Bonding layer 1246 may include an oxide (e.g., SiO₂) layer 1256 with bonding pads 1266 (or metal plugs) formed in oxide layer 1256 as described above. One or more sidewall layers (not shown in FIG. 12C) may be between oxide layer 1256 and bonding pads 1266. Bonding pads 1266 may also include two or more sections that have different sizes, where a top portion 1272 may be larger than other portions of bonding pads 1266. Therefore, there may be a sufficiently large contact area between bonding pads 1236 and bonding pads 1266 even if there is some misalignment. The examples of bonding pad designs shown in FIGS. 12A-12C may reduce the dielectric bonding regions at the bonding surface, and thus may not have sufficient dielectric bonding strength. In addition, the large bonding pads may cause short between bonding pads of adjacent micro-LEDs if the misalignment is large.

As described above with respect to, for example, FIGS. 9A-9D, to bond the micro-LED device (e.g., on a III-V wafer) with the drive circuits (e.g., on a CMOS backplane) through wafer-level hybrid bonding, the bonding surfaces of the micro-LED wafer and the CMOS backplane may need to be planarized, for example, by chemical mechanical planarization (CMP) techniques or other techniques. The planarization of the bonding surfaces may cause dishing in the metal bonding pads. As such, there may be a void between a metal bonding pad on the micro-LED device and a corresponding metal bonding pad on the CMOS backplane due to the dishing on the two metal bonding pads. In some CMP processes, pad-slurry matching may be used to control the copper dishing and oxide erosion.

FIG. 13A illustrates an example of a wafer 1300 including bonding pads 1340 with dishing. Wafer 1300 may include a substrate 1310, such as a silicon substrate, a GaAs substrate, a sapphire substrate, or the like. Electrical or optoelectronic circuits 1320 may be formed on substrate 1310. A dielectric layer 1330 may be deposited on electrical or optoelectronic circuits 1320. Trenches may be etched in dielectric layer 1330 and may be filled with a metal material, such as copper, gold, or aluminum, to form bonding pads 1340. The top surface of the wafer 1300 may be planarized as described above to remove metal material on top of dielectric layer 1330 and form a smooth and flat bonding surface, which may be cleaned or activated for hybrid bonding as described above. The planarization process may cause dishing in bonding pads 1340.

FIG. 13B illustrates bonding pads 1342 with dishing in an example of a wafer 1302. In the illustrated example, the pitch of the two-dimensional array of bonding pads 1342 (e.g., for p-contacts) may be about 2 μm, and the diameter of each bonding pad 1342 may be about 0.75 or 0.8 μm. The depth of the dishing of bonding pads 1342 may be about 2 nm to about 2.5 nm.

FIG. 13C illustrates measured surface profiles of the example of wafer 1302 including copper bonding pads 1342 with dishing. A curve 1350 shows the height profile of a linear array of the two-dimensional array of bonding pads 1342. A curve 1360 shows the height profile of another linear array of the two-dimensional array of bonding pads 1342. FIG. 13C shows that the depth of the dishing of bonding pads 1342 may be about 2 nm to about 2.5 nm.

FIG. 14 illustrates an example of a wafer 1400 including copper bonding pads with dishing of different depths. In the illustrated example, wafer 1400 may be an 8-inch silicon wafer. The depth of the dishing at the center region 1410 of wafer 1400 may be about 2 nm. The depth of the dishing at a region 1420 of wafer 1400 may be about 2.5 nm. The depth of the dishing at the edge region 1430 of wafer 1400 may be about 3 nm.

FIGS. 15A and 15B illustrate an example of hybrid bonding of two wafers 1502 and 1504 including copper bonding pads with dishing. FIG. 15A shows wafers 1502 and 1504 before the hybrid bonding. Wafer 1502 may include a silicon substrate 1510 with drive circuits 1520 fabricated thereon. A dielectric layer 1530 (e.g., SiO₂) may be deposited on drive circuits 1520. Trenches may be etched in dielectric layer 1530 and may be filled with a metal material, such as copper, gold, or aluminum, to form bonding pads 1540. As described above, a barrier layer (e.g., a Ti, Ta, or W layer, not shown in FIG. 15A) may be formed on sidewalls of the trenches before depositing the metal material to reduce or prevent the diffusion of the metal material to other regions that may cause leakage. The top surface of wafer 1502 may be planarized as described above to remove metal material on top of dielectric layer 1530 and form a smooth and flat bonding surface, which may then be cleaned or activated for hybrid bonding as described above. The planarization process may cause dishing in bonding pads 1540 as shown in FIG. 15A.

Wafer 1504 may include, for example, a substrate 1550 (e.g., a GaAs substrate) with an array of micro-LEDs 1560 fabricated thereon. The array of micro-LEDs 1560 may include an n-type semiconductor layer, an active region, and a p-type semiconductor layer epitaxially grown on substrate 1550. The epitaxial layers may then be processed from the side of the p-type semiconductor layer to form individual mesa structures, back reflectors/sidewall reflectors, p-contacts 1566, and n-contacts 1564. A dielectric layer 1570 (e.g., SiO₂) may be deposited on p-contacts 1566 and n-contacts 1564. Trenches may be etched in dielectric layer 1570 and may be filled with a metal material, such as copper, gold, or aluminum, to form bonding pads 1580. As described above, at least one barrier layer (e.g., a Ti, Ta, or W layer, or a multiple barrier layer stacks, such as TiN/Ti, TaN/Ta, Ti/TiN, Ta/TaN, etc., not shown in FIG. 15A) may be formed on sidewalls of the trenches before depositing the metal material to reduce or prevent the diffusion of the metal material to other regions that may cause leakage. The top surface of wafer 1504 may be planarized as described above to remove metal material on top of dielectric layer 1570 and form a smooth and flat bonding surface, which may then be cleaned or activated for hybrid bonding as described above. The planarization process may cause dishing in bonding pads 1580 as shown in FIG. 15A.

FIG. 15B shows that wafer 1502 and wafer 1504 may be brought into contact. In some embodiments, compressive force may be applied to wafer 1502 and wafer 1504 such that the bonding surfaces of wafer 1502 and wafer 1504 are pressed against each other. Due to the surface activation and the dishing in the bonding pads 1540 and 1580, the dielectric material (e.g., SiO₂) of dielectric layer 1530 and the dielectric material (e.g., SiO₂) of dielectric layer 1570 may be in direct contact, and may react and form chemical bonds between them because the surface atoms may have dangling bonds or adsorbed hydroxyl groups and may be in unstable energy states after the activation. Thus, the dielectric material (e.g., SiO₂) of dielectric layer 1530 and the dielectric material (e.g., SiO₂) of dielectric layer 1570 may be bonded together with or without heat treatment or pressure. Because of the dishing in the bonding pads 1540 and 1580, there may be a void 1590 between a bonding pad 1540 on wafer 1502 and a corresponding bonding pad 1580 on wafer 1504. As such, there may not be electric connection or may only be a high-impedance electric connection between bonding pad 1540 and bonding pad 1580.

Annealing at an elevated temperature may be performed such that the metal bonding pads may expand to reduce or eliminate void 1590 and form a reliable metal connection. When the ratio between the volume of void 1590 caused by the dishing and the volume of the metal material in metal bonding pads (e.g., bonding pad 1540 and bonding pad 1580) is large, the annealing temperature may need to be high in order to cause sufficient expansion of the metal material to completely fill the void. Annealing the bonded wafer stack including different materials on different substrates at high temperature may cause large wafer bowing due to, for example, the different thermal expansion coefficients of the different materials, such as Si substrate of the CMOS backplane and GaAs (or sapphire) substrate of the micro-LED device. The wafer bowing may create defects in or damages to the bonded wafer stack, such as high stress, cracks, delamination, crystal dislocation slip (glide), cratering, and the like.

FIGS. 16A-16D illustrate an example of an annealing process for a wafer stack formed by hybrid bonding of two wafers including copper bonding pads with dishing. FIG. 16A shows a wafer stack 1600 that includes a first wafer 1602 (which may be similar to wafer 1502) and a second wafer 1604 (which may be similar to wafer 1504) bonded together by dielectric bonding at room temperature. Because of the dishing in bonding pads 1610 and 1620, there may be a void 1630 between a bonding pad 1610 on first wafer 1602 and a corresponding bonding pad 1620 on second wafer 1604.

FIG. 16B shows thermal annealing of wafer stack 1600 at elevated temperature(s). At sufficiently high annealing temperature(s), the metal material (e.g., copper, gold, or aluminum) in bonding pads 1610 and 1620 may expand to completely fill the void, and thus bonding pad 1610 may be bonded to bonding pad 1620 by metal bonds. As described above, annealing the bonded wafer stack 1600 including different materials on different substrates at high temperature may cause large wafer bowing due to, for example, the different CTEs of the different materials, such as Si substrate of first wafer 1602 (e.g., COS backplane) and GaAs (or sapphire) substrate of second wafer 1604. When the thickness of the substrate is high (e.g., before thinning or removing of the supporting substrate), the bowing may be more significant. For example, in some examples, the wafer bowing may be as high as above 500 μm to above 1000 μm for 200-mm wafers.

FIG. 16C shows that bonded wafer stack 1600 may be gradually cooled down to room temperature, where first wafer 1602 and second wafer 1604 may be flattened. The bowing and/or the subsequent flattening of wafer stack 1600 may create various defects or damages in the bonded wafer stack 1600 as described above.

FIG. 16D shows a temperature cycle during the hybrid bonding. The dielectric bonding may be performed at room temperature. The annealing may be performed at an elevated temperature, where the minimum annealing temperature may be determined based on the volume of the void caused by the dishing, the volume of the metal material in the metal bonding pads, the shape and/or the dimension of the metal bonding pads, and the like. For example, as described above with respect to FIG. 14, the depth of the dishing may be different at different regions of a wafer. Therefore, different minimum annealing temperatures may be applied to different regions of the wafer stack, rather than applying the same annealing temperature for the entire area of the wafer stack, in order to reduce the annealing temperature and the bowing caused by the high temperature annealing. In the example shown in FIG. 16D, during annealing, three different temperatures may be applied to, for example, three different regions of wafer stack 1600. In one example, the center region of wafer stack 1600 may have a lower dishing depth (e.g., about 2 nm in the example shown in FIG. 14), and thus an annealing temperature about 150° C. may be used. The peripheral regions of wafer stack 1600 may have a higher dishing depth (e.g., about 3 nm in the example shown in FIG. 14), and thus an annealing temperature about 250° C. may be used. The regions between the center region and the peripheral regions of wafer stack 1600 may have an intermediate dishing depth (e.g., about 2.5 nm), and thus an intermediate annealing temperature (e.g., about 200° C.) may be used. This non-uniform heating may mitigate overheating on the metal bonding pads with less dishing and the resulted delamination of the dielectric bonding (e.g., oxide-to-oxide bonding) at the higher annealing temperature for larger dishing. After annealing for a certain period of time, wafer stack 1600 may be cooled down gradually to room temperature.

FIG. 17 includes a chart 1700 illustrating examples of copper expansion at different annealing temperatures for different examples of copper bonding pads with different diameters and dishing depths. Each bonding pad shown in the examples may have a cylindrical shape with a substantially uniform diameter of about 750 nm or about 1000 nm, and may have a different dishing depth d_dishing, such as about 2 nm, about 2.5 nm, or about 3 nm. The height of the expansion of a bonding pad at an elevated temperature is d_expansion. The minimum annealing temperature is the temperature under which the height of the expansion d_expansion of the bonding pad is the same as the dishing depth d_dishing.

In the illustrated examples, for a bonding pad with a diameter about 750 nm and a dishing depth d_dishing about 2 nm, the ratio between d_expansion and d_dishing at different annealing temperatures may be shown by a curve 1710, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 225° C. For a bonding pad with a diameter about 750 nm and a dishing depth d_dishing about 2.5 nm, the ratio between d_expansion and d_dishing at different annealing temperatures may be shown by a curve 1720, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 250° C. For a bonding pad with a diameter about 750 nm and a dishing depth d_dishing about 3 nm, the ratio between d_expansion and d_dishing at different annealing temperatures may be shown by a curve 1730, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 300° C. Thus, for a given bonding pad, the higher the dishing depth d_dishing, the higher the minimum annealing temperature may need to be.

For a bonding pad with a diameter about 1000 nm and a dishing depth d_dishing about 2 nm, the ratio between d_expansion and d_dishing at different annealing temperatures may be shown by a curve 1740, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 175° C. For a bonding pad with a diameter about 1000 nm and a dishing depth d_dishing about 2.5 nm, the ratio between d_expansion and d_dishing at different annealing temperatures may be shown by a curve 1750, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 200° C. For a bonding pad with a diameter about 1000 nm and a dishing depth d_dishing about 3 nm, the ratio between d_expansion and d_dishing at different annealing temperatures may be shown by a curve 1760, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 250° C. Compared with bonding pads having smaller diameters, bonding pads with larger diameters can be annealed at a lower annealing temperature in order to eliminate dishing having a same depth.

FIG. 18 illustrates examples of wafer bowing of a hybrid-bonded wafer stacks at different annealing temperatures. A curve 1810 in FIG. 18 shows the wafer bowing of a hybrid-bonded wafer stack including a first wafer and a second wafer at different annealing temperatures, where the thickness of the first wafer is about 50 μm. A curve 1820 in FIG. 18 shows the wafer bowing of a hybrid-bonded wafer stack including a first wafer and a second wafer at different annealing temperatures, where the thickness of the first wafer is about 600 μm. Curves 1810 and 1820 show that the wafer bowing of a hybrid-bonded wafer stack can be very large at higher annealing temperatures, in particular, for thick wafers. Thus, it may be desirable to reduce the minimum annealing temperature in order to reduce wafer bowing and the associated defects in the circuits or damages to the bonded wafer stack.

According to certain embodiments, the total volume of a metal (e.g., Cu) bonding pad may be increased, while still ensuring the dielectric bonding strength, by making the base part of the metal bonding pad much larger than the contacting part (at the bonding surface) of metal bonding pad. As a result, the cross-sectional area at the bonding surface may remain relatively small to have a relatively large oxide bonding area for high dielectric bonding strength, even for small-pitch micro-LED device (e.g., less than about 5 μm, 3 μm, or 2 μm), while the total volume of the metal (e.g., Cu) bonding pad may be increased significantly, such that the annealing temperature can be reduced, for example, by about 50° C. or more. In addition, due to the smaller cross-sectional area of the metal bonding pads at the bonding surface, the barrier layer at the bonding surface can have a higher width, such that barrier layer trenching at the bonding surface and/or misalignment of the bonding pads may not cause metal diffusion into the dielectric layer.

FIGS. 19A-19G illustrate some examples of copper bonding pad designs for reducing annealing temperature and improving bonding strength according to certain embodiments. The copper bonding pads may have any suitable shape at the bonding surface and/or in a horizontal (x-y) cross-section, such as a circle, an oval, a triangle, a rectangle, a square, another polygon, or any other regular or irregular shape. Even though copper bonding pads are shown in the examples, other metals, such as gold or aluminum, may also be used for the metal interconnects and the bonding pads.

In the example shown in FIG. 19A, two bonding layers 1910 and 1940 on two wafers may need to be bonded together using hybrid bonding. Bonding layer 1910 may include a plurality of bonding pads 1920 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂). Each bonding pad 1920 may include two sections, where the top portion 1930 (at the bonding surface) may have a smaller diameter such that there may be a larger dielectric bonding area at the interface to improve the dielectric bonding strength and reduce the possibility of shorting to an adjacent pad on bonding layer 1940. The bottom (or base) portion of bonding pad 1920 may have a large diameter, and thus the total volume of the metal material in bonding pad 1920 may be high, even though the contact area of bonding pad 1920 at the bonding surface is small (which may also have a lower dishing depth after the surface planarization). Therefore, a lower annealing temperature may be used to eliminate the dishing and the void formed after the room temperature dielectric bonding. As described above, at least a barrier layer (not shown in FIG. 19A) may be formed between bonding pads 1920 and the dielectric material to prevent or reduce the diffusion of the metal material.

Similarly, bonding layer 1940 may include a plurality of bonding pads 1950 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂). Each bonding pad 1950 may include two sections, where the top portion 1960 (at the bonding surface) may have a smaller diameter such that there may be a larger dielectric bonding area at the interface to improve the dielectric bonding strength and reduce the possibility of shorting to an adjacent bonding pad on bonding layer 1910. The bottom (or base) portion of bonding pad 1950 may have a large diameter, and thus the total volume of the metal material in bonding pad 1950 may be high, even though the contact area of the bonding pad 1950 at the bonding surface is small (which may also have a lower dishing depth after the surface planarization). Thus, a lower annealing temperature can be used to eliminate the dishing and the void formed after the room temperature dielectric bonding. As described above, at least a barrier layer (not shown in FIG. 19A) may be formed between bonding pads 1950 and the dielectric material to prevent or reduce the diffusion of the metal material.

In the example shown in FIG. 19B, two bonding layers 1912 and 1942 on two wafers may need to be bonded together using hybrid bonding. Bonding layer 1912 may include a plurality of bonding pads 1922 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂). Each bonding pad 1922 may have a shape of truncated cone, where the top surface (at the bonding surface) may have a smaller diameter (and thus may have a lower dishing depth after the surface planarization) such that there may be a larger dielectric bonding area at the interface to improve the dielectric bonding strength and reduce the possibility of shorting to an adjacent pad on bonding layer 1942. The diameter of bonding pad 1922 may gradually increase as the distance from the bonding surface increases. The total volume of the metal material in bonding pad 1922 may be higher than a cylinder-shaped bonding pad having a diameter that is same as the diameter of bonding pad 1922 at the bonding surface. As described above, at least a barrier layer (not shown in FIG. 19B) may be formed between bonding pads 1920 and the dielectric material to prevent or reduce the diffusion of the metal material. Bonding layer 1942 may include a plurality of bonding pads 1952 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂), where each bonding pad 1952 may be similar to bonding pad 1922. Therefore, a lower annealing temperature can be used to eliminate the dishing and the void formed after the room temperature dielectric bonding.

In the example shown in FIG. 19C, two bonding layers 1914 and 1944 on two wafers may need to be bonded together using hybrid bonding. Bonding layer 1914 may include a plurality of bonding pads 1924 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂), where each bonding pad 1924 may have a cylinder shape with a small diameter (e.g., ≤about ½, ⅓, or ¼ of a pitch of the plurality of bonding pads 1924). As described above, at least a barrier layer (not shown in FIG. 19C) may be formed between bonding pads 1924 and the dielectric material to prevent or reduce the diffusion of the metal material. Bonding layer 1944 may include a plurality of bonding pads 1954 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂). As described above, at least a barrier layer (not shown in FIG. 19C) may be formed between bonding pads 1954 and the dielectric material. Each bonding pad 1954 may include two sections, where the top portion 1964 (at the bonding surface) may have a smaller diameter such that there may be a larger dielectric bonding area at the interface to improve the dielectric bonding strength and reduce the possibility of shorting to an adjacent pad on bonding layer 1914. The bottom (or base) portion of bonding pad 1954 may have a large diameter, and thus the total volume of the metal material in bonding pad 1954 may be high, even though the contact area of the bonding pad 1954 at the bonding surface is small (which may have a lower dishing depth after the surface planarization). Therefore, a lower annealing temperature can be used to eliminate the dishing and the void formed after the room temperature dielectric bonding. In some embodiments, bonding pads 1924 may be replaced with bonding pads 1922 or 1952.

In the example shown in FIG. 19D, two bonding layers 1916 and 1946 on two wafers may need to be bonded together using hybrid bonding. Bonding layer 1916 may include a plurality of bonding pads 1926 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂), where each bonding pad 1926 may have a cylinder shape with a larger diameter. As described above, at least a barrier layer (not shown in FIG. 19D) may be formed between bonding pads 1926 and the dielectric material to prevent or reduce the diffusion of the metal material. Bonding layer 1946 may include a plurality of bonding pads 1956 (e.g., copper pads) formed in a dielectric layer (e.g., SiO₂). As described above, at least a barrier layer (not shown in FIG. 19D) may be formed between bonding pads 1956 and the dielectric material. Each bonding pad 1956 may include two sections, where the top portion 1966 (at the bonding surface) may have a smaller diameter to reduce the possibility of shorting to an adjacent pad on bonding layer 1916. The bottom (or base) portion of bonding pad 1956 may have a large diameter, and thus the total volume of the metal material in bonding pad 1956 may be high, even though the contact area of the bonding pad 1956 at the bonding surface is small (which may have a lower dishing depth after the surface planarization). Therefore, a lower annealing temperature may be used to eliminate the dishing and the void formed after the room temperature dielectric bonding. In some embodiments, bonding pads 1926 may be replaced with bonding pads 1922 or 1952.

FIG. 19E shows two bonding layers 1911 and 1941 (on two wafers) bonded together through hybrid bonding. Bonding layer 1911 may include a plurality of metal (e.g., Cu, Au, or Al) bonding pads 1921 formed in a dielectric (e.g., SiO₂) layer, where each metal bonding pad 1921 may have a cylindrical shape. Bonding layer 1941 may include a plurality of metal (e.g., Cu, Au, or Al) bonding pads 1951 formed in a dielectric (e.g., SiO₂) layer. The dielectric material in bonding layer 1941 may be bonded to the dielectric material in bonding layer 1911 through room temperature dielectric bonding. Each metal bonding pad 1951 may have a truncated conic shape, and may be bonded to a metal bonding pad 1921. The bottom (or base) portion of metal bonding pad 1951 may have a large diameter, and thus the total volume of the metal material in metal bonding pad 1951 may be high, even though the contact area of metal bonding pad 1951 at the bonding surface is small (and thus may have a lower dishing depth after the surface planarization). Therefore, a lower annealing temperature can be used to eliminate the dishing and the void formed after the room temperature dielectric bonding.

FIG. 19F shows two bonding layers 1913 and 1943 (on two wafers) bonded together through hybrid bonding. Bonding layer 1913 may include a plurality of metal (e.g., Cu, Au, or Al) bonding pads 1923 formed in a dielectric (e.g., SiO₂) layer, where each metal bonding pad 1923 may have a cylindrical shape. Bonding layer 1943 may include a plurality of metal (e.g., Cu, Au, or Al) bonding pads 1953 formed in a dielectric (e.g., SiO₂) layer. The dielectric material in bonding layer 1943 may be bonded to the dielectric material in bonding layer 1913 through room temperature dielectric bonding. Each metal bonding pad 1953 may have a truncated conic shape, and may be bonded to a metal bonding pad 1923. The bottom (or base) portion of metal bonding pad 1953 may have a large diameter, and thus the total volume of the metal material in metal bonding pad 1953 may be high, even though the contact area of metal bonding pad 1953 at the bonding surface is small (and thus may have a lower dishing depth after the surface planarization). Metal bonding pad 1923 may also have a large diameter and thus a large volume. Therefore, a lower annealing temperature can be used to eliminate the dishing and the void formed after the room temperature dielectric bonding.

FIG. 19G shows two bonding layers 1915 and 1945 (on two wafers) bonded together through hybrid bonding. Bonding layer 1915 may include a plurality of metal (e.g., Cu, Au, or Al) bonding pads 1925 formed in a dielectric (e.g., SiO₂) layer. Each metal bonding pad 1925 may include two sections, where the top portion 1935 (at or close to the bonding surface) may have a smaller diameter, such that there may be a larger dielectric bonding area at the interface to improve the dielectric bonding strength and reduce the possibility of shorting to an adjacent metal bonding pad on bonding layer 1945. The bottom (or base) portion of metal bonding pad 1925 may have a large diameter, and thus the total volume of the metal material in metal bonding pad 1925 may be high, even though the contact area of metal bonding pad 1925 at the bonding surface is small (and thus may have a lower dishing depth after the surface planarization). Bonding layer 1945 may include a plurality of metal (e.g., Cu, Au, or Al) bonding pads 1955 formed in a dielectric (e.g., SiO₂) layer. The dielectric material in bonding layer 1945 may be bonded to the dielectric material in bonding layer 1915 through room temperature dielectric bonding. Each metal bonding pad 1955 may have a truncated conic shape, and may be bonded to a metal bonding pad 1925. The bottom (or base) portion of metal bonding pad 1955 may have a large diameter, and thus the total volume of the metal material in metal bonding pad 1955 may be high, even though the contact area of metal bonding pad 1955 at the bonding surface is small (and thus may have a lower dishing depth after the surface planarization). Therefore, a lower annealing temperature can be used to eliminate the dishing and the void formed after the room temperature dielectric bonding.

FIGS. 20A and 20B illustrate dimensions of examples of copper bonding pad designs according to certain embodiments. The example of bonding pad 2000 illustrated in FIG. 20A is an example of bonding pad 1920, 1950, 1954, or 1956 described above, and may include a metal material such as copper, gold, or aluminum. Bonding pad 2000 includes a base portion 2010 (the bottom portion) and a bonding portion 2020 (the top portion or the contact portion) that have different diameters and/or heights. Base portion 2010 may have a diameter D_b and a height H_b. Bonding portion 2020 may have a diameter D_t and a height H_t, and may have copper dishing with a depth H_dish at the bonding surface. The total height of bonding pad 2000 is H_pad. The total height of bonding pad 2000 is H_pad. Diameter D_b, height H_b, diameter D_t, and height H_t may be any suitable values determined based on, for example, the pitch of the ponding pad, dielectric bonding strength, depth H_dish, of the dishing, minimum annealing temperature, and the like.

The example of bonding pad 2002 illustrated in FIG. 20B is an example of bonding pads 1922 or 1952 described above, and may include a metal material such as copper, gold, or aluminum. Bonding pad 2002 may have a trapezoid shape in the cross-section (or a truncated cone shape in 3-D), where the top surface (at the bonding surface) may have a diameter D_t, and may have dishing with a depth H_dish. The diameter of bonding pad 2002 may gradually increase as the distance from the bonding surface increases. The diameter of bonding pad 2002 at the base (bottom) may be D_b. The total height of bonding pad 2002 is H_pad. Diameter D_b, and diameter D_t, may be any suitable values determined based on, for example, the pitch, dielectric bonding strength, depth H_dish of the dishing, minimum annealing temperature, and the like.

Table 1 shows parameters of examples of bonding pad design described above. The example of the reference design shown in Table 1 includes a cylinder-shaped copper bonding pad as shown in FIGS. 11A, 11B, and 15A-16C, where the height H_pad of the bonding pad is about 800 nm, and the bonding surface of the bonding pad may have a diameter D_t about 750 nm and a dishing depth H_dish about 2.5 nm. The example of bonding pad 2000 shown in Table 1 may also have a height H_pad about 800 nm, and the bonding surface of the bonding pad may have a diameter D_t about 750 nm and a dishing depth H_dish about 2.5 nm. The ratio between diameter D_t and diameter D_b of the example of bonding pad 2000 shown in Table 1 may be about 5:11, and the ratio between height H_t and height H_b of the example of bonding pad 2000 shown in Table 1 may be about 1:2. The example of bonding pad 2002 shown in Table 1 may also have a height H_pad about 800 nm, and the bonding surface of bonding pad 2002 may have a diameter D_t about 750 nm and a dishing depth H_dish about 2.5 nm. The ratio between diameter D_t and diameter D_b of the example of bonding pad 2002 shown in Table 1 may be about 5:11. Each of the three examples of bonding pad may be used in an array of copper bonding pads having a pitch about 2 μm.

TABLE 1 Parameters of examples of copper bonding pad designs Reference Bonding Bonding bonding pad pad 2000 pad 2002 D_t, nm 750 750 750 H_pad, nm 800 800 800 H_dish, nm 2.5 2.5 2.5 Pitch, nm 2,000 2,000 2,000 D_t😀_b 1 5:11 5:11 H_t:H_b N/A 1:2 N/A

FIG. 21 includes a chart 2100 illustrating copper expansion as a function of the annealing temperature for the examples of copper bonding pad design shown in Table 1 according to certain embodiments. The depth of the dishing in all three examples is about 2.5 nm. A curve 2110 in FIG. 21 shows the ratio between d_expansion and d_dishing in the reference bonding pad of Table 1 at different annealing temperatures, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 (completely filling the void) is about 250° C. A curve 2120 in FIG. 21 shows the ratio between d_expansion and d_dishing in the example of bonding pad 2002 of Table 1 at different annealing temperatures, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 225° C. A curve 2130 in FIG. 21 shows the ratio between d_expansion and d_dishing in the example of bonding pad 2000 of Table 1 at different annealing temperatures, where the minimum annealing temperature under which d_expansion/d_dishing reaches 1.0 is about 200° C. Thus, the minimum annealing temperature for eliminating the dishing in bonding pad 2000 may be about 50° C. lower than that for the reference design because of the larger volume of copper available for expansion in bonding pad 2000. The minimum annealing temperature for eliminating the dishing in bonding pad 2002 may be higher than that for bonding pad 2000 due to the slightly lower volume of copper available for expansion, but may be about 25° C. lower than that for the reference design because of the larger volume of copper available for expansion in bonding pad 2002 than in the reference design.

FIG. 22A illustrates an example of barrier layer trenching at a bonding surface. FIG. 22A shows a bonding layer 2200 that includes a copper bonding pad 2230 formed in a dielectric material layer 2210. Bonding layer 2200 also includes a barrier layer 2220 between copper bonding pad 2230 and the dielectric material of dielectric material layer 2210. Barrier layer 2220 may need to have a certain thickness in order to prevent the diffusion of copper from copper bonding pad 2230 to the dielectric material as described above. FIG. 22A shows that the planarization of the bonding surface of bonding layer 2200 may create barrier layer trenches 2222 near the bonding surface. As such, copper material in copper bonding pad 2230 may be in contact with the dielectric material, for example, when copper bonding pad 2230 expands during annealing.

FIG. 22B illustrates an example of barrier layer trenching at a bonding surface according to certain embodiments. FIG. 22B shows a bonding layer 2202 that includes a bonding pad 2232 formed in a dielectric material layer 2212. Bonding pad 2232 may include a base (bottom) portion that has a larger diameter and a top portion 2234 that has a smaller diameter as described above. Bonding layer 2202 also includes a barrier layer 2224 between bonding pad 2232 and the dielectric material of dielectric material layer 2212. Due to the smaller cross-sectional area of the top portion 2234 of bonding pads 2232 at the bonding surface, the barrier layer at the bonding surface can have a higher width, such that barrier layer trenching at the bonding surface and/or misalignment of the bonding pads may not cause metal diffusion into the dielectric layer. For example, FIG. 22B shows that, even though there may be barrier layer trenching at the bonding surface, there may still be some barrier layer material between bonding pad 2232 and the dielectric material of dielectric material layer 2212 to prevent metal diffusion.

FIG. 22C illustrates an example of bonding a bonding pad 2236 to a bonding pad 2232 according to certain embodiments. A bonding layer 2204 includes a dielectric layer 2214 and bonding pads 2236 formed in dielectric layer 2214 is bonded to bonding layer 2202 described above. A bonding layer 2204 may have a similar structure as bonding layer 2202. As illustrated, barrier layer trenching at the bonding surfaces and misalignment of the bonding pads in the two bonding layers may not cause metal diffusion into the dielectric layer due to the thicker barrier layers at or near the bonding surfaces.

FIG. 23 includes a flowchart 2300 illustrating an example of a process of hybrid bonding according to certain embodiments. The operations described in flowchart 2300 are for illustration purposes only and are not intended to be limiting. Other sequences of operations can also be performed according to alternative embodiments. For example, alternative embodiments may perform the operations in a different order. Moreover, the individual operations illustrated in FIG. 23 can include multiple sub-operations that can be performed in various sequences as appropriate for the individual operation. Furthermore, some operations can be added or removed depending on the particular applications. In some implementations, two or more operations may be performed in parallel. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

Operations at block 2310 may include fabricating a micro-LED wafer including an array of micro-LEDs and a first set of bonding pads in a first dielectric layer. Each bonding pad of the first set of bonding pads may have a non-uniform lateral cross-sectional area and may have a smallest lateral cross-sectional area at a first surface (the bonding surface). A pitch of the array of micro-LEDs may be less than about 10 μm, less than 5 μm, less than 3 μm, or less than 2 μm. A pitch of the first set of bonding pads may be less than about 10 μm, less than 5 μm, less than 3 μm, or less than 2 μm. The first set of bonding pads may include metal bonding pads, such as copper pads or aluminum pads. In some embodiments, each bonding pad of the first set of bonding pads includes a first section having a first diameter and a second section having a second diameter that is larger than the first diameter. A height of the first section may be less than a half or a third of a height of the second section. The first diameter may be less than three quarters or a half of the second diameter. In some embodiments, each bonding pad of the first set of bonding pads may have a shape of a truncated cone. A diameter of a top surface of the truncated cone may be less than about three quarters or a half of a diameter of a base of the truncated cone. Each bonding pad of the first set of bonding pads may be electrically connected to a respective micro-LED in the array of micro-LEDs.

Operations at block 2320 may include fabricating a CMOS backplane including a drive circuit and a second set of bonding pads in a second dielectric layer. Each bonding pad of the second set of bonding pads may be characterized by a non-uniform lateral cross-sectional area and may have a smallest lateral cross-sectional area at a second surface (the bonding surface). A pitch of the second set of bonding pads may be less than about 10 μm, less than 5 μm, less than 3 μm, or less than 2 μm. The second set of bonding pads may include metal bonding pads, such as copper pads, gold pads, or aluminum pads. In some embodiments, each bonding pad of the second set of bonding pads may include a first section having a first diameter and a second section having a second diameter that is larger than the first diameter. A height of the first section may be less than a half or a third of a height of the second section. The first diameter may be less than three quarters or a half of the second diameter. In some embodiments, each bonding pad of the second set of bonding pads may have a shape of a truncated cone. A diameter of a top surface of the truncated cone may be less than about three quarters or a half of a diameter of a base of the truncated cone. Each bonding pad of the second set of bonding pads may be electrically connected to a respective micro-LED in the array of micro-LEDs through a corresponding bonding pad of the first set of bonding pads.

Operations at block 2330 may include bonding the first dielectric layer on the micro-LED wafer to the second dielectric layer on the CMOS backplane through dielectric bonding at a first temperature, such as a room temperature or another temperature below 50° C. As described above, before bonding, the bonding surface of the micro-LED wafer and the bonding surface of the CMOS backplane may be planarized, cleaned, and/or activated. The bond pads may have dishing after the planarization, and thus the bonded wafer stack may include voids between corresponding bonding pads.

Operations at block 2340 may include annealing the micro-LED wafer and the CMOS backplane at a second temperature higher than the first temperature to bond the first set of bonding pads to the second set of bonding pads (e.g., through thermal expansion). The second temperature may be below about 250° C., at or below about 200° C., or at or below about 150° C. The annealing may cause the expansion of the metal material (e.g., copper) of the bonding pads to fill the voids and for metallic bonds.

Optional operations at block 2350 may include forming a plurality of light extraction structures on the micro-LED wafer, such as micro-lenses, nano-structures, gratings, and the like, as described above with respect to, for example, FIG. 10.

According to certain embodiments, metal interconnects with larger heights may alternatively or additionally be used to provide more metal material and lower the annealing temperature for minimizing dishing and void. The thicker dielectric layer in which the metal interconnects are formed may be deposited at higher deposition temperatures, such as greater than about 300° C. (e.g., between about 350° C. and about 400° C.) for PECVD or greater than about 120° C. (e.g., between about 150° C. and about 250° C.) for inductively-coupled plasma enhanced chemical vapor deposition (ICPECVD). The high deposition temperatures may lead to larger wafer bowing at room temperature for Si, GaAs, or other wafers. In some embodiments, to reduce the wafer bow and warp (e.g., to less than about ±25 μm) for high precision bonding with high yield, an additional strain compensation layer, such as a SiN layer, a diamond like carbon (DLC) layer, and the like, may be deposited on the backside of the LED wafer and/or the backside of the Si wafer. In some embodiments, to reduce the wafer bow and wrap, local annealing inside laser spots may be performed by scanning a laser beam over the wafer, rather than performing a full wafer level annealing (e.g., at or below 250° C.).

FIG. 24A illustrates an example of a micro-LED array 2400 according to certain embodiments. FIG. 24B illustrates a cross-sectional view of the example of micro-LED array 2400 according to certain embodiments. Micro-LED array 2400 may include a two-dimensional array of micro-LEDs arranged in a plurality of columns and rows. FIG. 24A shows individual p-contacts 2440 for the micro-LEDs in micro-LED array 2400, and two shared n-contacts 2430 near two edges of micro-LED array 2400. FIG. 24B shows the cross-section along a line 2402.

In the example shown in FIG. 24B, micro-LED array 2400 may include an n-type semiconductor layer 2410, an active layer 2412 that may include one or more quantum wells, and a p-type semiconductor layer 2414. Layers 2410, 2412, and 2414 may be etched to form individual mesa structures. A patterned dielectric layer 2420 (e.g., SiN) may be formed on the surfaces of the mesa structures as a barrier layer, and an n-contact 2430 may be formed on the exposed n-type semiconductor layer 2410. A metal (e.g., aluminum) layer 2424 may be formed on dielectric layer 2420 and n-contact 2430. P-contacts 2440 may be formed on p-type semiconductor layers 2414 of the mesa structures. Regions between the mesa structures may be filled with a dielectric material 2426, such as SiO₂. Metal interconnects 2450 (e.g., Cu, Au, or Al interconnects) may be formed in a dielectric (e.g., SiO₂, SiN, or SiCN) layer 2452 to connect to p-contacts 2440 and n-contact 2430. A barrier and/or metal seed layer 2454 (e.g., TiN/Ti or TaN/Ta) may be between metal interconnects 2450 and dielectric layer 2452. A patterned current spreading layer 2460 may be formed on the bottom surface of n-type semiconductor layer to provide additional n-contacts near each individual micro-LEDs. Light extraction structures 2470 (e.g., micro-lenses) may be formed on the exposed regions of n-type semiconductor layer 2410.

In some embodiments, patterned current spreading layer 2460 and light extraction structures 2470 may be formed on n-type semiconductor layer 2410 after micro-LED array 2400 is bonded to a driver circuit fabricated on a silicon wafer as described below, such that the silicon wafer may be used as the handle wafer and the processes can be performed from the side of n-type semiconductor layer 2410.

FIG. 24C illustrates an example of a device 2405 including a micro-LED array (e.g., micro-LED array 2400) bonded to a CMOS backplane 2480 according to certain embodiments. CMOS backplane 2480 may include a substrate 2482, such as a silicon substrate. CMOS integrated circuits 2484, such as micro-LED driving circuits, may be fabricated on substrate 2482. CMOS backplane 2480 may also include metal (e.g., Cu, Au, or Al) interconnects 2486 formed in a dielectric (e.g., SiO₂, SiN, or SiCN) layer 2488. Micro-LED array 2400 and CMOS backplane 2480 may be bonded such that metal interconnects 2450 and metal interconnects 2486 may be bonded together and dielectric layer 2452 and dielectric layer 2488 may be bonded together.

In some embodiments, micro-LED array 2400 may be bonded to CMOS backplane 2480 using a die-to-wafer or wafer-to-wafer hybrid bonding process disclosed herein. For example, the surface of the micro-LED array wafer and the surface of the CMOS backplane wafer may be cleaned and then activated by a low temperature (e.g., room temperature) plasma surface activation process. The surface-activated wafers may be aligned and pre-bonded at low temperature (e.g., room temperature) to bond the dielectric layer on the surface of the micro-LED wafer to the dielectric layer on the surface of the CMOS backplane wafer. The pre-bonded wafers may then be annealed at an elevated temperature, such as between about 150° C. and about 350° C., to bond metal pads on the micro-LED wafer to the metal pads on the CMOS backplane wafer.

FIG. 25A illustrates an example of a micro-LED array 2500 according to certain embodiments. FIG. 25B illustrates a cross-sectional view of the example of micro-LED array 2500 shown in FIG. 25A according to certain embodiments. Micro-LED array 2500 may include a two-dimensional array of micro-LEDs arranged in a plurality of columns and rows. FIG. 25A shows individual p-contacts 2540 for the micro-LEDs in micro-LED array 2500, two shared n-contacts 2530 near two edges of micro-LED array 2500, and n-contacts 2532 adjacent and between the mesa structures of individual micro-LEDs. FIG. 25B shows the cross-section along a line 2504.

In the example shown in FIG. 25B, micro-LED array 2500 may include an n-type semiconductor layer 2510, an active layer 2512 that may include one or more quantum wells, and a p-type semiconductor layer 2514. Layers 2510, 2512, and 2514 may be etched to form individual mesa structures. A patterned dielectric layer 2520 (e.g., SiN) may be formed on the surfaces of the mesa structures as a barrier layer, and n-contacts 2530 and 2532 may be formed on the exposed n-type semiconductor layer 2510. The cross-sectional view along line 2504 in FIG. 25B shows n-contacts 2532 at locations where there may be larger gaps between adjacent mesa structures, such as the center of the diagonal line (e.g., along line 2504) between two adjacent mesa structures that are not in a same column or row of the two-dimensional micro-LED array 2500. In embodiments where the micro-LED may have a large pitch, n-contacts 2532 may also be at locations between adjacent mesa structures in a same row or column. A metal (e.g., aluminum) layer 2524 may be formed on dielectric layer 2520 and n-contacts 2530 and 2532. P-contacts 2540 may be formed on p-type semiconductor layers 2514 of the mesa structures. Regions between the mesa structures may be filled with a dielectric material 2526, such as SiO₂. Metal (e.g., Cu, Au, or Al) interconnects 2550 may be formed in a dielectric (e.g., SiO₂, SiN, or SiCN) layer 2552 to connect to p-contacts 2540 and n-contact 2530. A barrier and/or metal seed layer 2554 (e.g., TiN/Ti or TaN/Ta) may be between metal interconnects 2550 and dielectric layer 2552. Light extraction structures 2560 (e.g., micro-lenses) may be formed in n-type semiconductor layer 2510.

In some embodiments, light extraction structures 2560 may be formed on n-type semiconductor layer 2510 after micro-LED array 2500 is bonded to a driver circuit fabricated on a silicon wafer as described below, such that the silicon wafer may be used as the handle wafer and the processes can be performed from the side of n-type semiconductor layer 2510.

FIG. 25C illustrates an example of a device 2505 including a micro-LED array (e.g., micro-LED array 2500) bonded to a CMOS backplane 2580 according to certain embodiments. CMOS backplane 2580 may include a substrate 2582, such as a silicon substrate. CMOS integrated circuits 2584, such as micro-LED driving circuits, may be fabricated on substrate 2582. CMOS backplane 2580 may also include metal (e.g., Cu, Au, or Al) interconnects 2586 formed in a dielectric (e.g., SiO₂, SiN, or SiCN) layer 2588. Micro-LED array 2500 and CMOS backplane 2580 may be bonded such that metal interconnects 2550 and metal interconnects 2586 may be bonded together and dielectric layer 2552 and dielectric layer 2588 may be bonded together. FIG. 25C shows the cross-sectional view of micro-LED array 2500 long a line 2502 and thus n-contacts 2532 may not be viewable.

In some embodiments, micro-LED array 2500 may be bonded to CMOS backplane 2580 using a die-to-wafer or wafer-to-wafer hybrid bonding process disclosed herein. For example, the surface of the micro-LED array wafer and the surface of the CMOS backplane wafer may be cleaned and then activated by a low temperature (e.g., room temperature) plasma surface activation process. The surface-activated wafers may be aligned and pre-bonded at low temperature (e.g., room temperature) to bond the dielectric layer on the surface of the micro-LED wafer to the dielectric layer on the surface of the CMOS backplane wafer. The pre-bonded wafers may then be annealed at an elevated temperature, such as about 150° C. to about 350° C., to bond metal pads on the micro-LED wafer to the metal pads on the CMOS backplane wafer.

Embodiments disclosed herein may be used to implement components of an artificial reality system or may be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, for example, a virtual reality, an augmented reality, a mixed reality, a hybrid reality, or some combination and/or derivatives thereof. Artificial reality content may include completely generated content or generated content combined with captured (e.g., real-world) content. The artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of which may be presented in a single channel or in multiple channels (such as stereo video that produces a three-dimensional effect to the viewer). Additionally, in some embodiments, artificial reality may also be associated with applications, products, accessories, services, or some combination thereof, that are used to, for example, create content in an artificial reality and/or are otherwise used in (e.g., perform activities in) an artificial reality. The artificial reality system that provides the artificial reality content may be implemented on various platforms, including an HMD connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.

FIG. 26 is a simplified block diagram of an example electronic system 2600 of an example near-eye display (e.g., HMD device) for implementing some of the examples disclosed herein. Electronic system 2600 may be used as the electronic system of an HMD device or other near-eye displays described above. In this example, electronic system 2600 may include one or more processor(s) 2610 and a memory 2620. Processor(s) 2610 may be configured to execute instructions for performing operations at a number of components, and can be, for example, a general-purpose processor or microprocessor suitable for implementation within a portable electronic device. Processor(s) 2610 may be communicatively coupled with a plurality of components within electronic system 2600. To realize this communicative coupling, processor(s) 2610 may communicate with the other illustrated components across a bus 2640. Bus 2640 may be any subsystem adapted to transfer data within electronic system 2600. Bus 2640 may include a plurality of computer buses and additional circuitry to transfer data.

Memory 2620 may be coupled to processor(s) 2610. In some embodiments, memory 2620 may offer both short-term and long-term storage and may be divided into several units. Memory 2620 may be volatile, such as static random access memory (SRAM) and/or dynamic random access memory (DRAM) and/or non-volatile, such as read-only memory (ROM), flash memory, and the like. Furthermore, memory 2620 may include removable storage devices, such as secure digital (SD) cards. Memory 2620 may provide storage of computer-readable instructions, data structures, program modules, and other data for electronic system 2600. In some embodiments, memory 2620 may be distributed into different hardware modules. A set of instructions and/or code might be stored on memory 2620. The instructions might take the form of executable code that may be executable by electronic system 2600, and/or might take the form of source and/or installable code, which, upon compilation and/or installation on electronic system 2600 (e.g., using any of a variety of generally available compilers, installation programs, compression/decompression utilities, etc.), may take the form of executable code.

In some embodiments, memory 2620 may store a plurality of application modules 2622 through 2624, which may include any number of applications. Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications. The applications may include a depth sensing function or eye tracking function. Application modules 2622-2624 may include particular instructions to be executed by processor(s) 2610. In some embodiments, certain applications or parts of application modules 2622-2624 may be executable by other hardware modules 2680. In certain embodiments, memory 2620 may additionally include secure memory, which may include additional security controls to prevent copying or other unauthorized access to secure information.

In some embodiments, memory 2620 may include an operating system 2625 loaded therein. Operating system 2625 may be operable to initiate the execution of the instructions provided by application modules 2622-2624 and/or manage other hardware modules 2680 as well as interfaces with a wireless communication subsystem 2630 which may include one or more wireless transceivers. Operating system 2625 may be adapted to perform other operations across the components of electronic system 2600 including threading, resource management, data storage control and other similar functionality.

Wireless communication subsystem 2630 may include, for example, an infrared communication device, a wireless communication device and/or chipset (such as a Bluetooth® device, an IEEE 802.11 device, a Wi-Fi device, a WiMax device, cellular communication facilities, etc.), and/or similar communication interfaces. Electronic system 2600 may include one or more antennas 2634 for wireless communication as part of wireless communication subsystem 2630 or as a separate component coupled to any portion of the system. Depending on desired functionality, wireless communication subsystem 2630 may include separate transceivers to communicate with base transceiver stations and other wireless devices and access points, which may include communicating with different data networks and/or network types, such as wireless wide-area networks (WWANs), wireless local area networks (WLANs), or wireless personal area networks (WPANs). A WWAN may be, for example, a WiMax (IEEE 802.16) network. A WLAN may be, for example, an IEEE 802.11x network. A WPAN may be, for example, a Bluetooth network, an IEEE 802.15x, or some other types of network. The techniques described herein may also be used for any combination of WWAN, WLAN, and/or WPAN. Wireless communications subsystem 2630 may permit data to be exchanged with a network, other computer systems, and/or any other devices described herein. Wireless communication subsystem 2630 may include a means for transmitting or receiving data, such as identifiers of HMD devices, position data, a geographic map, a heat map, photos, or videos, using antenna(s) 2634 and wireless link(s) 2632. Wireless communication subsystem 2630, processor(s) 2610, and memory 2620 may together comprise at least a part of one or more of a means for performing some functions disclosed herein.

Embodiments of electronic system 2600 may also include one or more sensors 2690. Sensor(s) 2690 may include, for example, an image sensor, an accelerometer, a pressure sensor, a temperature sensor, a proximity sensor, a magnetometer, a gyroscope, an inertial sensor (e.g., a module that combines an accelerometer and a gyroscope), an ambient light sensor, or any other similar module operable to provide sensory output and/or receive sensory input, such as a depth sensor or a position sensor. For example, in some implementations, sensor(s) 2690 may include one or more inertial measurement units (IMUs) and/or one or more position sensors. An IMU may generate calibration data indicating an estimated position of the HMD device relative to an initial position of the HMD device, based on measurement signals received from one or more of the position sensors. A position sensor may generate one or more measurement signals in response to motion of the HMD device. Examples of the position sensors may include, but are not limited to, one or more accelerometers, one or more gyroscopes, one or more magnetometers, another suitable type of sensor that detects motion, a type of sensor used for error correction of the IMU, or any combination thereof. The position sensors may be located external to the IMU, internal to the IMU, or any combination thereof. At least some sensors may use a structured light pattern for sensing.

Electronic system 2600 may include a display module 2660. Display module 2660 may be a near-eye display, and may graphically present information, such as images, videos, and various instructions, from electronic system 2600 to a user. Such information may be derived from one or more application modules 2622-2624, virtual reality engine 2626, one or more other hardware modules 2680, a combination thereof, or any other suitable means for resolving graphical content for the user (e.g., by operating system 2625). Display module 2660 may use LCD technology, LED technology (including, for example, OLED, ILED, μ-LED, AMOLED, TOLED, etc.), light emitting polymer display (LPD) technology, or some other display technology.

Electronic system 2600 may include a user input/output module 2670. User input/output module 2670 may allow a user to send action requests to electronic system 2600. An action request may be a request to perform a particular action. For example, an action request may be to start or end an application or to perform a particular action within the application. User input/output module 2670 may include one or more input devices. Example input devices may include a touchscreen, a touch pad, microphone(s), button(s), dial(s), switch(es), a keyboard, a mouse, a game controller, or any other suitable device for receiving action requests and communicating the received action requests to electronic system 2600. In some embodiments, user input/output module 2670 may provide haptic feedback to the user in accordance with instructions received from electronic system 2600. For example, the haptic feedback may be provided when an action request is received or has been performed.

Electronic system 2600 may include a camera 2650 that may be used to take photos or videos of a user, for example, for tracking the user's eye position. Camera 2650 may also be used to take photos or videos of the environment, for example, for VR, AR, or MR applications. Camera 2650 may include, for example, a complementary metal-oxide-semiconductor (CMOS) image sensor with a few millions or tens of millions of pixels. In some implementations, camera 2650 may include two or more cameras that may be used to capture 3-D images.

In some embodiments, electronic system 2600 may include a plurality of other hardware modules 2680. Each of other hardware modules 2680 may be a physical module within electronic system 2600. While each of other hardware modules 2680 may be permanently configured as a structure, some of other hardware modules 2680 may be temporarily configured to perform specific functions or temporarily activated. Examples of other hardware modules 2680 may include, for example, an audio output and/or input module (e.g., a microphone or speaker), a near field communication (NFC) module, a rechargeable battery, a battery management system, a wired/wireless battery charging system, etc. In some embodiments, one or more functions of other hardware modules 2680 may be implemented in software.

In some embodiments, memory 2620 of electronic system 2600 may also store a virtual reality engine 2626. Virtual reality engine 2626 may execute applications within electronic system 2600 and receive position information, acceleration information, velocity information, predicted future positions, or any combination thereof of the HMD device from the various sensors. In some embodiments, the information received by virtual reality engine 2626 may be used for producing a signal (e.g., display instructions) to display module 2660. For example, if the received information indicates that the user has looked to the left, virtual reality engine 2626 may generate content for the HMD device that mirrors the user's movement in a virtual environment. Additionally, virtual reality engine 2626 may perform an action within an application in response to an action request received from user input/output module 2670 and provide feedback to the user. The provided feedback may be visual, audible, or haptic feedback. In some implementations, processor(s) 2610 may include one or more GPUs that may execute virtual reality engine 2626.

In various implementations, the above-described hardware and modules may be implemented on a single device or on multiple devices that can communicate with one another using wired or wireless connections. For example, in some implementations, some components or modules, such as GPUs, virtual reality engine 2626, and applications (e.g., tracking application), may be implemented on a console separate from the head-mounted display device. In some implementations, one console may be connected to or support more than one HMD.

In alternative configurations, different and/or additional components may be included in electronic system 2600. Similarly, functionality of one or more of the components can be distributed among the components in a manner different from the manner described above. For example, in some embodiments, electronic system 2600 may be modified to include other system environments, such as an AR system environment and/or an MR environment.

The methods, systems, and devices discussed above are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, in alternative configurations, the methods described may be performed in an order different from that described, and/or various stages may be added, omitted, and/or combined. Also, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Also, technology evolves and, thus, many of the elements are examples that do not limit the scope of the disclosure to those specific examples.

Specific details are given in the description to provide a thorough understanding of the embodiments. However, embodiments may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. This description provides example embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the preceding description of the embodiments will provide those skilled in the art with an enabling description for implementing various embodiments. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the present disclosure.

Also, some embodiments were described as processes depicted as flow diagrams or block diagrams. Although each may describe the operations as a sequential process, many of the operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional steps not included in the figure. Furthermore, embodiments of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the associated tasks may be stored in a computer-readable medium such as a storage medium. Processors may perform the associated tasks.

It will be apparent to those skilled in the art that substantial variations may be made in accordance with specific requirements. For example, customized or special-purpose hardware might also be used, and/or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both. Further, connection to other computing devices such as network input/output devices may be employed.

With reference to the appended figures, components that can include memory can include non-transitory machine-readable media. The term “machine-readable medium” and “computer-readable medium” may refer to any storage medium that participates in providing data that causes a machine to operate in a specific fashion. In embodiments provided hereinabove, various machine-readable media might be involved in providing instructions/code to processing units and/or other device(s) for execution. Additionally or alternatively, the machine-readable media might be used to store and/or carry such instructions/code. In many implementations, a computer-readable medium is a physical and/or tangible storage medium. Such a medium may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and/or optical media such as compact disk (CD) or digital versatile disk (DVD), punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and/or code. A computer program product may include code and/or machine-executable instructions that may represent a procedure, a function, a subprogram, a program, a routine, an application (App), a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements.

Those of skill in the art will appreciate that information and signals used to communicate the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Terms, “and” and “or” as used herein, may include a variety of meanings that are also expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of” if used to associate a list, such as A, B, or C, can be interpreted to mean A, B, C, or any combination of A, B, and/or C, such as AB, AC, BC, AA, ABC, AAB, AABBCCC, or the like.

Further, while certain embodiments have been described using a particular combination of hardware and software, it should be recognized that other combinations of hardware and software are also possible. Certain embodiments may be implemented only in hardware, or only in software, or using combinations thereof. In one example, software may be implemented with a computer program product containing computer program code or instructions executable by one or more processors for performing any or all of the steps, operations, or processes described in this disclosure, where the computer program may be stored on a non-transitory computer readable medium. The various processes described herein can be implemented on the same processor or different processors in any combination.

Where devices, systems, components or modules are described as being configured to perform certain operations or functions, such configuration can be accomplished, for example, by designing electronic circuits to perform the operation, by programming programmable electronic circuits (such as microprocessors) to perform the operation such as by executing computer instructions or code, or processors or cores programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof. Processes can communicate using a variety of techniques, including, but not limited to, conventional techniques for inter-process communications, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, subtractions, deletions, and other modifications and changes may be made thereunto without departing from the broader spirit and scope as set forth in the claims. Thus, although specific embodiments have been described, these are not intended to be limiting. Various modifications and equivalents are within the scope of the following claims.