Intel Patent | Predictive viewport renderer and foveated color compressor

Patent: Predictive viewport renderer and foveated color compressor

Drawings: Click to check drawins

Publication Number: 20210350597

Publication Date: 20211111

Applicant: Intel

Assignee: Intel Corporation

Abstract

An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.

Claims

  1. (canceled)

  2. A computing system comprising: a graphics processor; a central processing unit; and a memory including a set of instructions, which when executed by one or more of the graphics processor or the central processing unit, cause the computing system to: identify one or more optical characteristic of a head-mounted display (HMD); divide a frame into viewports based on the one or more optical characteristic of the HMD; and assign the viewports one or more of different priorities, different resolutions or different frame rates.

  3. The system of claim 2, wherein the instructions, when executed, cause the computing system to: assign the viewports the different priorities; and adjust the different priorities based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  4. The system of claim 2, wherein the instructions, when executed, cause the computing system to: adjust sizes of the viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  5. The system of claim 4, wherein the instructions, when executed, cause the computing system to: enlarge a size of a first viewport of the viewports that is to include the area of focus; and increase a priority of the priorities associated with the first viewport.

  6. The system of claim 2, wherein the instructions, when executed, cause the computing system to: determine a render order to render the viewports based on the different priorities; determine resolutions to render the viewports based on the different priorities; and determine frame rates of the viewports based on the different priorities.

  7. The system of claim 2, wherein the instructions, when executed, cause the computing system to: load a distortion map associated with the HMD; and divide the frame into the viewports based on the distortion map.

  8. An apparatus comprising: a memory; and logic communicatively coupled to the memory, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality logic hardware, the logic communicatively coupled to the memory to: identify one or more optical characteristic of a head-mounted display (HMD); divide a frame into viewports based on the one or more optical characteristic of the HMD; and assign the viewports one or more of different priorities, different resolutions or different frame rates.

  9. The apparatus of claim 8, wherein the logic coupled to the memory is to: assign the viewports the different priorities; and adjust the different priorities based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  10. The apparatus of claim 8, wherein the logic coupled to the memory is to: adjust sizes of the viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  11. The apparatus of claim 10, wherein the logic coupled to the memory is to: enlarge a size of a first viewport of the viewports that is to include the area of focus; and increase a priority of the priorities associated with the first viewport.

  12. The apparatus of claim 8, wherein the logic coupled to the memory is to: determine a render order to render the viewports based on the different priorities; determine resolutions to render the viewports based on the different priorities; and determine frame rates of the viewports based on the different priorities.

  13. The apparatus of claim 8, wherein the logic coupled to the memory is to: load a distortion map associated with the HMD; and divide the frame into the viewports based on the distortion map.

  14. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing device, cause the computing device to: identify one or more optical characteristic of a head-mounted display (HMD); divide a frame into viewports based on the one or more optical characteristic of the HMD; and assign the viewports one or more of different priorities, different resolutions or different frame rates.

  15. The at least one non-transitory computer readable storage medium of claim 14, wherein the instructions, when executed, cause the computing device to: assign the viewports the different priorities; and adjust the different priorities based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  16. The at least one non-transitory computer readable storage medium of claim 14, wherein the instructions, when executed, cause the computing device to: adjust sizes of the viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  17. The at least one non-transitory computer readable storage medium of claim 16, wherein the instructions, when executed, cause the computing device to: enlarge a size of a first viewport of the viewports that is to include the area of focus; and increase a priority of the priorities associated with the first viewport.

  18. The at least one non-transitory computer readable storage medium of claim 14, wherein the instructions, when executed, cause the computing device to: determine a render order to render the viewports based on the different priorities; determine resolutions to render the viewports based on the different priorities; and determine frame rates of the viewports based on the different priorities.

  19. The at least one non-transitory computer readable storage medium of claim 14, wherein the instructions, when executed, cause the computing device to: load a distortion map associated with the HMD; and divide the frame into the viewports based on the distortion map.

  20. A method comprising: identifying one or more optical characteristic of a head-mounted display (HMD); dividing a frame into viewports based on the one or more optical characteristic of the HMD; and assigning the viewports one or more of different priorities, different resolutions or different frame rates.

  21. The method of claim 20, further comprising: assigning the viewports the different priorities; and adjusting the different priorities based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  22. The method of claim 20, further comprising: adjusting sizes of the viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information or content information.

  23. The method of claim 22, further comprising: enlarging a size of a first viewport of the viewports that includes the area of focus; and increasing a priority of the priorities associated with the first viewport.

  24. The method of claim 20, further comprising: determining a render order to render the viewports based on the different priorities; determining resolutions to render the viewports based on the different priorities; and determining frame rates of the viewports based on the different priorities.

  25. The method of claim 20, further comprising: loading a distortion map associated with the HMD; and dividing the frame into the viewports based on the distortion map.

Description

CROSS-REFERENCE WITH RELATED APPLICATIONS

[0001] The present application claims the benefit of priority to U.S. Non-Provisional patent application Ser. No. 16/533,920 filed on Aug. 7, 2019 which claims priority to U.S. Non-Provisional patent application Ser. No. 15/476,990 filed on Apr. 1, 2017.

TECHNICAL FIELD

[0002] Embodiments generally relate to data processing and to graphics processing via a graphics processing unit. More particularly, embodiments relate to a predictive viewport renderer and foveated color compressor.

BACKGROUND OF THE DESCRIPTION

[0003] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data. Various settings, parameters, and configurations may be applied to operations on graphics data. Fovea may refer to a small depression in the retina of the eye where visual acuity may be highest. The center of the field of vision may be focused in this region, where retinal cones may be particularly concentrated. In the context of some graphics applications, a fovea or a foveated area may correspond to an area of focus in an image or display.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:

[0005] FIG. 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] FIG. 2A-2D illustrate a parallel processor components, according to an embodiment;

[0007] FIGS. 3A-3B are block diagrams of graphics multiprocessors, according to embodiments;

[0008] FIG. 4A-4F illustrate an exemplary architecture in which a plurality of GPUs are communicatively coupled to a plurality of multi-core processors;

[0009] FIG. 5 illustrates a graphics processing pipeline, according to an embodiment;

[0010] FIG. 6A is a block diagram of an example of an electronic processing system according to an embodiment;

[0011] FIG. 6B is a block diagram of an example of an image compressor apparatus according to an embodiment;

[0012] FIGS. 6C to 6D are flowcharts of an example of a method of compressing an image according to an embodiment;

[0013] FIGS. 6E to 6J are illustrative drawings of examples of color masks according to various embodiments;

[0014] FIGS. 6K and 6L are illustrative drawings of examples of a color mask applied to an image area according to an embodiment;

[0015] FIG. 6M is a block diagram of another example of an electronic processing system according to an embodiment;

[0016] FIG. 7A is a block diagram of an example of another electronic processing system according to an embodiment;

[0017] FIG. 7B is a block diagram of an example of a graphics viewport apparatus according to an embodiment;

[0018] FIG. 7C is a flowchart of an example of a method of processing a frame according to an embodiment;

[0019] FIG. 7D to 7H are illustrative drawings of examples of frames divided into viewports according to an embodiment;

[0020] FIGS. 8A to 8B are block diagrams of examples of another electronic processing system and a viewport processor apparatus according to embodiments;

[0021] FIG. 8C is a flowchart of an example of a method of updating a frame according to an embodiment;

[0022] FIG. 9A is a block diagram of an example of another electronic processing system according to an embodiment;

[0023] FIG. 9B is a block diagram of an example of a motion processor apparatus according to an embodiment;

[0024] FIGS. 9C to 9D are flowcharts of an example of a method of placing a virtual object according to an embodiment;

[0025] FIG. 10A is a block diagram of an example of another electronic processing system according to an embodiment;

[0026] FIG. 10B is a block diagram of an example of another electronic processing system according to an embodiment;

[0027] FIG. 11 is an illustration of an example of a head mounted display (HMD) system according to an embodiment;

[0028] FIG. 12 is a block diagram of an example of the functional components included in the HMD system of FIG. 11 according to an embodiment;

[0029] FIG. 13 is a block diagram of an example of a general processing cluster included in a parallel processing unit according to an embodiment;

[0030] FIG. 14 is a conceptual illustration of an example of a graphics processing pipeline that may be implemented within a parallel processing unit, according to an embodiment;

[0031] FIG. 15 is a block diagram of an example of a streaming multi-processor according to an embodiment;

[0032] FIGS. 16-18 are block diagrams of an example of an overview of a data processing system according to an embodiment;

[0033] FIG. 19 is a block diagram of an example of a graphics processing engine according to an embodiment;

[0034] FIGS. 20-22 are block diagrams of examples of execution units according to an embodiment;

[0035] FIG. 23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0036] FIGS. 24A-24B are block diagrams of examples of graphics pipeline programming according to an embodiment;

[0037] FIG. 25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0038] FIG. 26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0039] FIG. 27 is a block diagram of an example of a system on a chip integrated circuit according to an embodiment.

DETAILED DESCRIPTION

[0040] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

System Overview

[0041] FIG. 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processor(s) 102 and a system memory 104 communicating via an interconnection path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processor(s) 102. The memory hub 105 couples with an I/O subsystem 111 via a communication link 106. The I/O subsystem 111 includes an I/O hub 107 that can enable the computing system 100 to receive input from one or more input device(s) 108. Additionally, the I/O hub 107 can enable a display controller, which may be included in the one or more processor(s) 102, to provide outputs to one or more display device(s) 110A. In one embodiment the one or more display device(s) 110A coupled with the I/O hub 107 can include a local, internal, or embedded display device.

[0042] In one embodiment the processing subsystem 101 includes one or more parallel processor(s) 112 coupled to memory hub 105 via a bus or other communication link 113. The communication link 113 may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. In one embodiment the one or more parallel processor(s) 112 form a computationally focused parallel or vector processing system that an include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. In one embodiment the one or more parallel processor(s) 112 form a graphics processing subsystem that can output pixels to one of the one or more display device(s) 110A coupled via the I/O Hub 107. The one or more parallel processor(s) 112 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 110B.

[0043] Within the I/O subsystem 111, a system storage unit 114 can connect to the I/O hub 107 to provide a storage mechanism for the computing system 100. An I/O switch 116 can be used to provide an interface mechanism to enable connections between the I/O hub 107 and other components, such as a network adapter 118 and/or wireless network adapter 119 that may be integrated into the platform, and various other devices that can be added via one or more add-in device(s) 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[0044] The computing system 100 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, may also be connected to the I/O hub 107. Communication paths interconnecting the various components in FIG. 1 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interfaces and/or protocol(s), such as the NV-Link high-speed interconnect, or interconnect protocols known in the art.

[0045] In one embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s), 112 memory hub 105, processor(s) 102, and I/O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0046] It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, may be modified as desired. For instance, in some embodiments, system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I/O hub 107 or directly to one of the one or more processor(s) 102, rather than to the memory hub 105. In other embodiments, the I/O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processor(s) 102 attached via multiple sockets, which can couple with two or more instances of the parallel processor(s) 112.

[0047] Some of the particular components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology for components similar to those illustrated in FIG. 1. For example, the memory hub 105 may be referred to as a Northbridge in some architectures, while the I/O hub 107 may be referred to as a Southbridge.

[0048] FIG. 2A illustrates a parallel processor 200, according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). The illustrated parallel processor 200 is a variant of the one or more parallel processor(s) 112 shown in FIG. 1, according to an embodiment.

[0049] In one embodiment the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I/O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I/O unit 204 may be directly connected to other devices. In one embodiment the I/O unit 204 connects with other devices via the use of a hub or switch interface, such as memory hub 105. The connections between the memory hub 105 and the I/O unit 204 form a communication link 113. Within the parallel processing unit 202, the I/O unit 204 connects with a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands directed to performing processing operations and the memory crossbar 216 receives commands directed to performing memory operations.

[0050] When the host interface 206 receives a command buffer via the I/O unit 204, the host interface 206 can direct work operations to perform those commands to a front end 208. In one embodiment the front end 208 couples with a scheduler 210, which is configured to distribute commands or other work items to a processing cluster array 212. In one embodiment the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before tasks are distributed to the processing clusters of the processing cluster array 212. In one embodiment the scheduler 210 is implemented via firmware logic executing on a microcontroller. The microcontroller implemented scheduler 210 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing array 212. In one embodiment, the host software can prove workloads for scheduling on the processing array 212 via one of multiple graphics processing doorbells. The workloads can then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0051] The processing cluster array 212 can include up to “N” processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N of the processing cluster array 212 can execute a large number of concurrent threads. The scheduler 210 can allocate work to the clusters 214A-214N of the processing cluster array 212 using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. The scheduling can be handled dynamically by the scheduler 210, or can be assisted in part by compiler logic during compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 can be allocated for processing different types of programs or for performing different types of computations.

[0052] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment the processing cluster array 212 is configured to perform general-purpose parallel compute operations. For example, the processing cluster array 212 can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0053] In one embodiment the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments in which the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 can include additional logic to support the execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 can transfer data from system memory via the I/O unit 204 for processing. During processing the transferred data can be stored to on-chip memory (e.g., parallel processor memory 222) during processing, then written back to system memory.

[0054] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations to multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 can be configured to perform different types of processing. For example a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214A-214N for further processing.

[0055] During operation, the processing cluster array 212 can receive processing tasks to be executed via the scheduler 210, which receives commands defining processing tasks from front end 208. For graphics processing operations, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 210 may be configured to fetch the indices corresponding to the tasks or may receive the indices from the front end 208. The front end 208 can be configured to ensure the processing cluster array 212 is configured to a valid state before the workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

[0056] Each of the one or more instances of the parallel processing unit 202 can couple with parallel processor memory 222. The parallel processor memory 222 can be accessed via the memory crossbar 216, which can receive memory requests from the processing cluster array 212 as well as the I/O unit 204. The memory crossbar 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 222. In one implementation the number of partition units 220A-220N is configured to be equal to the number of memory units, such that a first partition unit 220A has a corresponding first memory unit 224A, a second partition unit 220B has a corresponding memory unit 224B, and an Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0057] In various embodiments, the memory units 224A-224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Persons skilled in the art will appreciate that the specific implementation of the memory units 224A-224N can vary, and can be selected from one of various conventional designs. Render targets, such as frame buffers or texture maps may be stored across the memory units 224A-224N, allowing partition units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0058] In one embodiment, any one of the clusters 214A-214N of the processing cluster array 212 can process data that will be written to any of the memory units 224A-224N within parallel processor memory 222. The memory crossbar 216 can be configured to transfer the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I/O unit 204, as well as a connection to a local instance of the parallel processor memory 222, enabling the processing units within the different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment the memory crossbar 216 can use virtual channels to separate traffic streams between the clusters 214A-214N and the partition units 220A-220N.

[0059] While a single instance of the parallel processing unit 202 is illustrated within the parallel processor 200, any number of instances of the parallel processing unit 202 can be included. For example, multiple instances of the parallel processing unit 202 can be provided on a single add-in card, or multiple add-in cards can be interconnected. The different instances of the parallel processing unit 202 can be configured to inter-operate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example and in one embodiment, some instances of the parallel processing unit 202 can include higher precision floating point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems.

[0060] FIG. 2B is a block diagram of a partition unit 220, according to an embodiment. In one embodiment the partition unit 220 is an instance of one of the partition units 220A-220N of FIG. 2A. As illustrated, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operations unit). The L2 cache 221 is a read/write cache that is configured to perform load and store operations received from the memory crossbar 216 and ROP 226. Read misses and urgent write-back requests are output by L2 cache 221 to frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment the frame buffer interface 225 interfaces with one of the memory units in parallel processor memory, such as the memory units 224A-224N of FIG. 2 (e.g., within parallel processor memory 222).

[0061] In graphics applications, the ROP 226 is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments the ROP 226 includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0062] In some embodiments, the ROP 226 is included within each processing cluster (e.g., cluster 214A-214N of FIG. 2) instead of within the partition unit 220. In such embodiment, read and write requests for pixel data are transmitted over the memory crossbar 216 instead of pixel fragment data. The processed graphics data may be displayed on a display device, such as one of the one or more display device(s) 110 of FIG. 1, routed for further processing by the processor(s) 102, or routed for further processing by one of the processing entities within the parallel processor 200 of FIG. 2A.

[0063] FIG. 2C is a block diagram of a processing cluster 214 within a parallel processing unit, according to an embodiment. In one embodiment the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. The processing cluster 214 can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of the processing clusters. Unlike a SIMD execution regime, where all processing engines typically execute identical instructions, SIMT execution allows different threads to more readily follow divergent execution paths through a given thread program. Persons skilled in the art will understand that a SIMD processing regime represents a functional subset of a SIMT processing regime.

[0064] Operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages execution of those instructions via a graphics multiprocessor 234 and/or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of differing architectures may be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within a processing cluster 214. The graphics multiprocessor 234 can process data and a data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations, including other shader units. The pipeline manager 232 can facilitate the distribution of processed data by specifying destinations for processed data to be distributed vis the data crossbar 240.

[0065] Each graphics multiprocessor 234 within the processing cluster 214 can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. The functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In one embodiment the same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present.

[0066] The instructions transmitted to the processing cluster 214 constitutes a thread. A set of threads executing across the set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within the graphics multiprocessor 234 processing can be performed over consecutive clock cycles. In one embodiment multiple thread groups can be executed concurrently on a graphics multiprocessor 234.

[0067] In one embodiment the graphics multiprocessor 234 includes an internal cache memory to perform load and store operations. In one embodiment, the graphics multiprocessor 234 can forego an internal cache and use a cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 also has access to L2 caches within the partition units (e.g., partition units 220A-220N of FIG. 2) that are shared among all processing clusters 214 and may be used to transfer data between threads. The graphics multiprocessor 234 may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. Any memory external to the parallel processing unit 202 may be used as global memory. Embodiments in which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 can share common instructions and data, which may be stored in the L1 cache 308.

[0068] Each processing cluster 214 may include an MMU 245 (memory management unit) that is configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2. The MMU 245 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile (talk more about tiling) and optionally a cache line index. The MMU 245 may include address translation lookaside buffers (TLB) or caches that may reside within the graphics multiprocessor 234 or the L1 cache or processing cluster 214. The physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. The cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0069] In graphics and computing applications, a processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from the L1 cache within graphics multiprocessor 234 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs processed tasks to the data crossbar 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 216. A preROP 242 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 234, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 220A-220N of FIG. 2). The preROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translations.

[0070] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, e.g., graphics multiprocessor 234, texture units 236, preROPs 242, etc., may be included within a processing cluster 214. Further, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of the processing cluster 214. In one embodiment, each processing cluster 214 can be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0071] FIG. 2D shows a graphics multiprocessor 234, according to one embodiment. In such embodiment the graphics multiprocessor 234 couples with the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including but not limited to an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load/store units 266. The GPGPU cores 262 and load/store units 266 are coupled with cache memory 272 and shared memory 270 via a memory and cache interconnect 268.

[0072] In one embodiment, the instruction cache 252 receives a stream of instructions to execute from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group assigned to a different execution unit within GPGPU core 262. An instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. The address mapping unit 256 can be used to translate addresses in the unified address space into a distinct memory address that can be accessed by the load/store units 266.

[0073] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 262, load/store units 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps being executed by the graphics multiprocessor 324.

[0074] The GPGPU cores 262 can each include floating point units (FPUs) and/or integer arithmetic logic units (ALUs) that are used to execute instructions of the graphics multiprocessor 324. The GPGPU cores 262 can be similar in architecture or can differ in architecture, according to embodiments. For example and in one embodiment, a first portion of the GPGPU cores 262 include a single precision FPU and an integer ALU while a second portion of the GPGPU cores include a double precision FPU. In one embodiment the FPUs can implement the IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. The graphics multiprocessor 324 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In one embodiment one or more of the GPGPU cores can also include fixed or special function logic.

[0075] In one embodiment the GPGPU cores 262 include SIMD logic capable of performing a single instruction on multiple sets of data. In one embodiment GPGPU cores 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. Multiple threads of a program configured for the SIMT execution model can executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0076] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load/store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU cores 262, thus data transfer between the GPGPU cores 262 and the register file 258 is very low latency. The shared memory 270 can be used to enable communication between threads that execute on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as a data cache for example, to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program managed cached. Threads executing on the GPGPU cores 262 can programmatically store data within the shared memory in addition to the automatically cached data that is stored within the cache memory 272.

[0077] FIGS. 3A-3B illustrate additional graphics multiprocessors, according to embodiments. The illustrated graphics multiprocessors 325, 350 are variants of the graphics multiprocessor 234 of FIG. 2C. The illustrated graphics multiprocessors 325, 350 can be configured as a streaming multiprocessor (SM) capable of simultaneous execution of a large number of execution threads.

[0078] FIG. 3A shows a graphics multiprocessor 325 according to an additional embodiment. The graphics multiprocessor 325 includes multiple additional instances of execution resource units relative to the graphics multiprocessor 234 of FIG. 2D. For example, the graphics multiprocessor 325 can include multiple instances of the instruction unit 332A-332B, register file 334A-334B, and texture unit(s) 344A-344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU core 336A-336B, GPGPU core 337A-337B, GPGPU core 338A-338B) and multiple sets of load/store units 340A-340B. In one embodiment the execution resource units have a common instruction cache 330, texture and/or data cache memory 342, and shared memory 346.

[0079] The various components can communicate via an interconnect fabric 327. In one embodiment the interconnect fabric 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325. In one embodiment the interconnect fabric 327 is a separate, high-speed network fabric layer upon which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect fabric 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can each communicate with shared memory 346 via the interconnect fabric 327. The interconnect fabric 327 can arbitrate communication within the graphics multiprocessor 325 to ensure a fair bandwidth allocation between components.

[0080] FIG. 3B shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resource includes multiple instruction units, register files, GPGPU cores, and load store units, as illustrated in FIG. 2D and FIG. 3A. The execution resources 356A-356D can work in concert with texture unit(s) 360A-360D for texture operations, while sharing an instruction cache 354, and shared memory 362. In one embodiment the execution resources 356A-356D can share an instruction cache 354 and shared memory 362, as well as multiple instances of a texture and/or data cache memory 358A-358B. The various components can communicate via an interconnect fabric 352 similar to the interconnect fabric 327 of FIG. 3A.

[0081] Persons skilled in the art will understand that the architecture described in FIGS. 1, 2A-2D, and 3A-3B are descriptive and not limiting as to the scope of the present embodiments. Thus, the techniques described herein may be implemented on any properly configured processing unit, including, without limitation, one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units, such as the parallel processing unit 202 of FIG. 2, as well as one or more graphics processors or special purpose processing units, without departure from the scope of the embodiments described herein.

[0082] In some embodiments a parallel processor or GPGPU as described herein is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.

[0083] Techniques for GPU to Host Processor Interconnection

[0084] FIG. 4A illustrates an exemplary architecture in which a plurality of GPUs 410-413 are communicatively coupled to a plurality of multi-core processors 405-406 over high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support a communication throughput of 4 GB/s, 30 GB/s, 80 GB/s or higher, depending on the implementation. Various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0085] In addition, in one embodiment, two or more of the GPUs 410-413 are interconnected over high-speed links 444-445, which may be implemented using the same or different protocols/links than those used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected over high speed link 433 which may be symmetric multi-processor (SMP) buses operating at 20 GB/s, 30 GB/s, 120 GB/s or higher. Alternatively, all communication between the various system components shown in FIG. 4A may be accomplished using the same protocols/links (e.g., over a common interconnection fabric). As mentioned, however, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0086] In one embodiment, each multi-core processor 405-406 is communicatively coupled to a processor memory 401-402, via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 over GPU memory interconnects 450-453, respectively. The memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example, and not limitation, the processor memories 401-402 and GPU memories 420-423 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and/or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the memories may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0087] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to a particular memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the “effective address” space) is distributed among all of the various physical memories. For example, processor memories 401-402 may each comprise 64 GB of the system memory address space and GPU memories 420-423 may each comprise 32 GB of the system memory address space (resulting in a total of 256 GB addressable memory in this example).

[0088] FIG. 4B illustrates additional details for an interconnection between a multi-core processor 407 and a graphics acceleration module 446 in accordance with one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card which is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0089] The illustrated processor 407 includes a plurality of cores 460A-460D, each with a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data which are not illustrated to avoid obscuring the underlying principles of the invention (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). The caches 462A-462D may comprise level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the caching hierarchy and shared by sets of the cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches are shared by two adjacent cores. The processor 407 and the graphics accelerator integration module 446 connect with system memory 441, which may include processor memories 401-402

[0090] Coherency is maintained for data and instructions stored in the various caches 462A-462D, 456 and system memory 441 via inter-core communication over a coherence bus 464. For example, each cache may have cache coherency logic/circuitry associated therewith to communicate to over the coherence bus 464 in response to detected reads or writes to particular cache lines. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping/coherency techniques are well understood by those of skill in the art and will not be described in detail here to avoid obscuring the underlying principles of the invention.

[0091] In one embodiment, a proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. In particular, an interface 435 provides connectivity to the proxy circuit 425 over high-speed link 440 (e.g., a PCIe bus, NVLink, etc.) and an interface 437 connects the graphics acceleration module 446 to the link 440.

[0092] In one implementation, an accelerator integration circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU with a plurality of graphics processing engines 431-432, N or the graphics processing engines 431-432, N may be individual GPUs integrated on a common package, line card, or chip.

[0093] In one embodiment, the accelerator integration circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching the virtual/effective to physical/real address translations. In one implementation, a cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in cache 438 and graphics memories 433-434, N is kept coherent with the core caches 462A-462D, 456 and system memory 411. As mentioned, this may be accomplished via proxy circuit 425 which takes part in the cache coherency mechanism on behalf of cache 438 and memories 433-434, N (e.g., sending updates to the cache 438 related to modifications/accesses of cache lines on processor caches 462A-462D, 456 and receiving updates from the cache 438).

[0094] A set of registers 445 store context data for threads executed by the graphics processing engines 431-432, N and a context management circuit 448 manages the thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore contexts of the various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be execute by a graphics processing engine). For example, on a context switch, the context management circuit 448 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore the register values when returning to the context. In one embodiment, an interrupt management circuit 447 receives and processes interrupts received from system devices.

[0095] In one implementation, virtual/effective addresses from a graphics processing engine 431 are translated to real/physical addresses in system memory 411 by the MMU 439. One embodiment of the accelerator integration circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and/or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407 or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources may be subdivided into “slices” which are allocated to different VMs and/or applications based on the processing requirements and priorities associated with the VMs and/or applications.

[0096] Thus, the accelerator integration circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integration circuit 436 may provide virtualization facilities for the host processor to manage virtualization of the graphics processing engines, interrupts, and memory management.

[0097] Because hardware resources of the graphics processing engines 431-432, N are mapped explicitly to the real address space seen by the host processor 407, any host processor can address these resources directly using an effective address value. One function of the accelerator integration circuit 436, in one embodiment, is the physical separation of the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0098] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are coupled to each of the graphics processing engines 431-432, N, respectively. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and/or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0099] In one embodiment, to reduce data traffic over link 440, biasing techniques are used to ensure that the data stored in graphics memories 433-434, M is data which will be used most frequently by the graphics processing engines 431-432, N and preferably not used by the cores 460A-460D (at least not frequently). Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not the graphics processing engines 431-432, N) within the caches 462A-462D, 456 of the cores and system memory 411.

[0100] FIG. 4C illustrates another embodiment in which the accelerator integration circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly over the high-speed link 440 to the accelerator integration circuit 436 via interface 437 and interface 435 (which, again, may be utilize any form of bus or interface protocol). The accelerator integration circuit 436 may perform the same operations as those described with respect to FIG. 4B, but potentially at a higher throughput given its close proximity to the coherency bus 462 and caches 462A-462D, 426.

[0101] One embodiment supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization). The latter may include programming models which are controlled by the accelerator integration circuit 436 and programming models which are controlled by the graphics acceleration module 446.

[0102] In one embodiment of the dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. The single application can funnel other application requests to the graphics engines 431-432, N, providing virtualization within a VM/partition.

[0103] In the dedicated-process programming models, the graphics processing engines 431-432, N, may be shared by multiple VM/application partitions. The shared models require a system hypervisor to virtualize the graphics processing engines 431-432, N to allow access by each operating system. For single-partition systems without a hypervisor, the graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, N to provide access to each process or application.

[0104] For the shared programming model, the graphics acceleration module 446 or an individual graphics processing engine 431-432, N selects a process element using a process handle. In one embodiment, process elements are stored in system memory 411 and are addressable using the effective address to real address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (that is, calling system software to add the process element to the process element linked list). The lower 16-bits of the process handle may be the offset of the process element within the process element linked list.

[0105] FIG. 4D illustrates an exemplary accelerator integration slice 490. As used herein, a “slice” comprises a specified portion of the processing resources of the accelerator integration circuit 436. Application effective address space 482 within system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to GPU invocations 481 from applications 480 executed on the processor 407. A process element 483 contains the process state for the corresponding application 480. A work descriptor (WD) 484 contained in the process element 483 can be a single job requested by an application or may contain a pointer to a queue of jobs. In the latter case, the WD 484 is a pointer to the job request queue in the application’s address space 482.

[0106] The graphics acceleration module 446 and/or the individual graphics processing engines 431-432, N can be shared by all or a subset of the processes in the system. Embodiments of the invention include an infrastructure for setting up the process state and sending a WD 484 to a graphics acceleration module 446 to start a job in a virtualized environment.

[0107] In one implementation, the dedicated-process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or an individual graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integration circuit 436 for the owning partition and the operating system initializes the accelerator integration circuit 436 for the owning process at the time when the graphics acceleration module 446 is assigned.

[0108] In operation, a WD fetch unit 491 in the accelerator integration slice 490 fetches the next WD 484 which includes an indication of the work to be done by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 may be stored in registers 445 and used by the MMU 439, interrupt management circuit 447 and/or context management circuit 446 as illustrated. For example, one embodiment of the MMU 439 includes segment/page walk circuitry for accessing segment/page tables 486 within the OS virtual address space 485. The interrupt management circuit 447 may process interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, an effective address 493 generated by a graphics processing engine 431-432, N is translated to a real address by the MMU 439.

[0109] In one embodiment, the same set of registers 445 are duplicated for each graphics processing engine 431-432, N and/or graphics acceleration module 446 and may be initialized by the hypervisor or operating system. Each of these duplicated registers may be included in an accelerator integration slice 490. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

TABLE-US-00001 TABLE 1 Hypervisor Initialized Registers 1 Slice Control Register 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0110] Exemplary registers that may be initialized by the operating system are shown in Table 2.

TABLE-US-00002 TABLE 2 Operating System Initialized Registers 1 Process and Thread Identification 2 Effective Address (EA) Context Save/Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work descriptor

[0111] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and/or graphics processing engine 431-432, N. It contains all the information a graphics processing engine 431-432, N requires to do its work or it can be a pointer to a memory location where the application has set up a command queue of work to be completed.

[0112] FIG. 4E illustrates additional details for one embodiment of a shared model. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 which virtualizes the graphics acceleration module engines for the operating system 495.

[0113] The shared programming models allow for all or a subset of processes from all or a subset of partitions in the system to use a graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced shared and graphics directed shared.

[0114] In this model, the system hypervisor 496 owns the graphics acceleration module 446 and makes its function available to all operating systems 495. For a graphics acceleration module 446 to support virtualization by the system hypervisor 496, the graphics acceleration module 446 may adhere to the following requirements: 1) An application’s job request must be autonomous (that is, the state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) An application’s job request is guaranteed by the graphics acceleration module 446 to complete in a specified amount of time, including any translation faults, or the graphics acceleration module 446 provides the ability to preempt the processing of the job. 3) The graphics acceleration module 446 must be guaranteed fairness between processes when operating in the directed shared programming model.

[0115] In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save/restore area pointer (CSRP). The graphics acceleration module 446 type describes the targeted acceleration function for the system call. The graphics acceleration module 446 type may be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to use for the current process. The value passed to the operating system is similar to an application setting the AMR. If the accelerator integration circuit 436 and graphics acceleration module 446 implementations do not support a User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current Authority Mask Override Register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 containing the effective address of an area in the application’s address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if no state is required to be saved between jobs or when a job is preempted. The context save/restore area may be pinned system memory.

[0116] Upon receiving the system call, the operating system 495 may verify that the application 480 has registered and been given the authority to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

TABLE-US-00003 TABLE 3 OS to Hypervisor Call Parameters 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked). 3 An effective address (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 The virtual address of the storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN)

[0117] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and been given the authority to use the graphics acceleration module 446. The hypervisor 496 then puts the process element 483 into the process element linked list for the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

TABLE-US-00004 TABLE 4 Process Element Information 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked). 3 An effective address (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 The virtual address of the storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters. 9 A state register (SR) value 10 A logical partition ID (LPID) 11 A real address (RA) hypervisor accelerator utilization record pointer 12 The Storage Descriptor Register (SDR)

[0118] In one embodiment, the hypervisor initializes a plurality of accelerator integration slice 490 registers 445.

[0119] As illustrated in FIG. 4F, one embodiment of the invention employs a unified memory addressable via a common virtual memory address space used to access the physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on the GPUs 410-413 utilize the same virtual/effective memory address space to access the processors memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual/effective address space is allocated to the processor memory 401, a second portion to the second processor memory 402, a third portion to the GPU memory 420, and so on. The entire virtual/effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0120] In one embodiment, bias/coherence management circuitry 494A-494E within one or more of the MMUs 439A-439E ensures cache coherence between the caches of the host processors (e.g., 405) and the GPUs 410-413 and implements biasing techniques indicating the physical memories in which certain types of data should be stored. While multiple instances of bias/coherence management circuitry 494A-494E are illustrated in FIG. 4F, the bias/coherence circuitry may be implemented within the MMU of one or more host processors 405 and/or within the accelerator integration circuit 436.

[0121] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering the typical performance drawbacks associated with full system cache coherence. The ability to GPU-attached memory 420-423 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. This arrangement allows the host processor 405 software to setup operands and access computation results, without the overhead of tradition I/O DMA data copies. Such traditional copies involve driver calls, interrupts and memory mapped I/O (MMIO) accesses that are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU attached memory 420-423 without cache coherence overheads can be critical to the execution time of an offloaded computation. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by a GPU 410-413. The efficiency of operand setup, the efficiency of results access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offload.

[0122] In one implementation, the selection of between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which may be a page-granular structure (i.e., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. The bias table may be implemented in a stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in the GPU 410-413 (e.g., to cache frequently/recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0123] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed prior the actual access to the GPU memory, causing the following operations. First, local requests from the GPU 410-413 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 420-423. Local requests from the GPU that find their page in host bias are forwarded to the processor 405 (e.g., over a high-speed link as discussed above). In one embodiment, requests from the processor 405 that find the requested page in host processor bias complete the request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to the GPU 410-413. The GPU may then transition the page to a host processor bias if it is not currently using the page.

[0124] The bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0125] One mechanism for changing the bias state employs an API call (e.g. OpenCL), which, in turn, calls the GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to the GPU directing it to change the bias state and, for some transitions, perform a cache flushing operation in the host. The cache flushing operation is required for a transition from host processor 405 bias to GPU bias, but is not required for the opposite transition.

[0126] In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 405. To access these pages, the processor 405 may request access from the GPU 410 which may or may not grant access right away, depending on the implementation. Thus, to reduce communication between the processor 405 and GPU 410 it is beneficial to ensure that GPU-biased pages are those which are required by the GPU but not the host processor 405 and vice versa.

[0127] Graphics Processing Pipeline

[0128] FIG. 5 illustrates a graphics processing pipeline 500, according to an embodiment. In one embodiment a graphics processor can implement the illustrated graphics processing pipeline 500. The graphics processor can be included within the parallel processing subsystems as described herein, such as the parallel processor 200 of FIG. 2, which, in one embodiment, is a variant of the parallel processor(s) 112 of FIG. 1. The various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of the parallel processing unit (e.g., parallel processing unit 202 of FIG. 2) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment/pixel processing unit 524. The functions of data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operations unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3) and a corresponding partition unit (e.g., partition unit 220A-220N of FIG. 2). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 can be performed by parallel processing logic within a general purpose processor (e.g., CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 can access on-chip memory (e.g., parallel processor memory 222 as in FIG. 2) via a memory interface 528, which may be an instance of the memory interface 218 of FIG. 2.

[0129] In one embodiment the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including the vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, lighting and transforming vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data that is stored in cache, local or system memory for use in processing the vertex data and may be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0130] A first instance of a primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 readings stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. The graphics primitives include triangles, line segments, points, patches, and so forth, as supported by various graphics processing application programming interfaces (APIs).

[0131] The tessellation control processing unit 508 treats the input vertices as control points for a geometric patch. The control points are transformed from an input representation from the patch (e.g., the patch’s bases) to a representation that is suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also compute tessellation factors for edges of geometric patches. A tessellation factor applies to a single edge and quantifies a view-dependent level of detail associated with the edge. A tessellation unit 510 is configured to receive the tessellation factors for edges of a patch and to tessellate the patch into multiple geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to a tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitives.

[0132] A second instance of a primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reading stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and calculate parameters used to rasterize the new graphics primitives.

[0133] In some embodiments the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs the parameters and vertices specifying new graphics primitives to primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by a viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data that is stored in parallel processor memory or system memory for use in processing the geometry data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs processed graphics primitives to a rasterizer 522.

[0134] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on the new graphics primitives to generate fragments and output those fragments and associated coverage data to the fragment/pixel processing unit 524. The fragment/pixel processing unit 524 is a programmable execution unit that is configured to execute fragment shader programs or pixel shader programs. The fragment/pixel processing unit 524 transforming fragments or pixels received from rasterizer 522, as specified by the fragment or pixel shader programs. For example, the fragment/pixel processing unit 524 may be programmed to perform operations included but not limited to texture mapping, shading, blending, texture correction and perspective correction to produce shaded fragments or pixels that are output to a raster operations unit 526. The fragment/pixel processing unit 524 can read data that is stored in either the parallel processor memory or the system memory for use when processing the fragment data. Fragment or pixel shader programs may be configured to shade at sample, pixel, tile, or other granularities depending on the sampling rate configured for the processing units.

[0135] The raster operations unit 526 is a processing unit that performs raster operations including, but not limited to stencil, z test, blending, and the like, and outputs pixel data as processed graphics data to be stored in graphics memory (e.g., parallel processor memory 222 as in FIG. 2, and/or system memory 104 as in FIG. 1, to be displayed on the one or more display device(s) 110 or for further processing by one of the one or more processor(s) 102 or parallel processor(s) 112. In some embodiments the raster operations unit 526 is configured to compress z or color data that is written to memory and decompress z or color data that is read from memory.

[0136] Foveated Color Compressor

[0137] Turning now to FIG. 6A, an embodiment of an electronic processing system 600 may include an application processor 611, persistent storage media 612 communicatively coupled to the application processor 611, and a parallel processing unit (PPU) 613 communicatively coupled to the persistent storage media 612 and the application processor 611. The PPU 613 may include an image compressor apparatus 614 as described herein (e.g. see FIG. 6B-6M).

[0138] Turning now to FIG. 6B, an embodiment of an image compressor apparatus 620 may include a focus identifier 621 to identify a focus area, and a color compressor 622 communicatively coupled to the focus identifier 621 to selectively compress color data based on the identified focus area. For example, the focus identifier 621 may be further configured to identify the focus area based on user gaze information. In some embodiments, the color compressor 622 may be further configured to selectively compress color data based on two or more successively surrounded, non-intersected regions related to the identified focus area. For example, the color compressor 622 may apply relatively less compression to an innermost region of the two or more successively surrounded, non-intersected regions as compared to an outer region of the two or more successively surrounded, non-intersected regions.

[0139] In some embodiments, the apparatus 620 may further include a frame buffer 623 communicatively coupled to the color compressor 622 to store image data including the color data, and a mask store 624 to store two or more color masks respectively corresponding to the two or more successively surrounded, non-intersected regions. For example, the color compressor 622 may apply the color mask to the frame buffer 623 to color compress the image data stored in the frame buffer 623.

[0140] In accordance with some embodiments, any of the above examples may further include a frame divider to divide a frame into two or more viewports, a viewport prioritizer communicatively coupled to the frame divider to prioritize the two or more viewports, a renderer communicatively coupled to the viewport prioritizer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter communicatively coupled to the renderer to transmit a completed rendered viewport, wherein the renderer is further to render another viewport of the frame at a same time as the viewport transmitter transmits the completed rendered viewport (e.g. as described in more detail in connection with FIGS. 7A to 7H below).

[0141] In accordance with some embodiments, any of the above examples may further include a motion detector to detect motion of a real object, a motion predictor communicatively coupled to the motion detector to predict a motion of the real object, and an object placer communicatively coupled to the motion detector and the motion predictor to place a virtual object relative to the real object based on the predicted motion of the real object viewport (e.g. as described in more detail in connection with FIGS. 9A to 9D, 10A, and 10B below).

[0142] Embodiments of each of the above application processor 611, persistent storage media 612, PPU 613, image compressor apparatus 614/620, focus identifier 621, color compressor 622, frame buffer 623, mask store 624, and other components may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic such as, for example, programmable logic arrays (PLAs), FPGAs, complex programmable logic devices (CPLDs), or in fixed-functionality logic hardware using circuit technology such as, for example, ASIC, complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof. Alternatively, or additionally, these components may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more operating system applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.

[0143] For example, the system 600 may include similar components and/or features as system 100, further configured to selectively compress color data based on an identified focus area. For example, the PPU 613 may include similar components and/or features as the parallel processor 200, further configured with an image compressor apparatus as described herein. The system 600 may also be adapted to work with a stereo head mounted system such as, for example, the system described in connection with FIGS. 11-15 below. In particular, the HMII 1100 described in more detail below may include a gaze tracker to provide gaze/focus information to the focus identifier 621.

[0144] Turning now to FIGS. 6C to 6D, an embodiment of a method 630 of compressing an image may include identifying a focus area at block 632, and selectively compressing color data based on the identified focus area at block 634. The method 630 may also include identifying the focus area based on user gaze information at block 636. In some embodiments, the method 630 may also include selectively compressing color data based on two or more successively surrounded, non-intersected regions related to the identified focus area at block 638. For example, the method 630 may include applying relatively less compression to an innermost region of the two or more successively surrounded, non-intersected regions as compared to an outer region of the two or more successively surrounded, non-intersected regions at block 640. In some embodiments, the method 630 may also include storing image data including the color data in a frame buffer at block 642, storing two or more color masks respectively corresponding to the two or more successively surrounded, non-intersected regions at block 644, and applying the color mask to the frame buffer to color compress the image data stored in the frame buffer at block 646.

[0145] Embodiments of the method 630 may be implemented in a system, apparatus, GPU, PPU, or a graphics processor pipeline apparatus such as, for example, those described herein. More particularly, hardware implementations of the method 630 may include configurable logic such as, for example, PLAs, FPGAs, CPLDs, or in fixed-functionality logic hardware using circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or additionally, the method 630 may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more operating system applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. For example, the method 630 may be implemented on a computer readable medium as described in connection with Examples 13 to 17 below.

[0146] For example, embodiments or portions of the method 630 may be implemented in applications (e.g. through an API) or driver software. Other embodiments or portions of the method 630 may be implemented in specialized code (e.g. shaders) to be executed on a GPU. Other embodiments or portions of the method 630 may be implemented in fixed function logic or specialized hardware (e.g. in the GPU).

[0147] Some embodiments may advantageously change color encoding for foveated rendering. For example, some embodiments may use color perception of the human visual system (HVS) to change encoding and compress color information in the frame buffer. The quality may change based on color perception. Some embodiments may advantageously save network bandwidth and power, which may be particularly useful for wireless virtual reality (VR) and encode. Some embodiments may provide a simple addition to foveated rendering to reduce color precision required for color representation. For example, if a system utilizes foveated rendering, gaze/eye tracking information may already be input to the CPU and/or GPU. Some embodiments may be used in combination with other foveated rendering techniques to add the benefit of color compression.

[0148] At a high level, some embodiments may use color perception information from the HVS to change the traits of the color representation based on where the user is looking. Focus cues may be limited to the focal region of where the user is looking. If the user is looking straight ahead they may see things in sharp focus. The focus may be based on what the user is looking at. With scenes or objects towards the periphery, the user may notice motion but not in sharp focus.

[0149] Some embodiments may include or get gaze information from an eye tracker to track the user’s eyes. Some embodiments may then use that gaze information to provide the most color information where the user is looking, and to degrade performance and color information away from the focal region. For example, color may be represented by 16-bit, 32-bit, etc. But the image/display does not need full precision if the user is not going to notice the difference in the color because they are not focusing on it. The user may perceive a color as red, but whether its maroon or scarlet or something else (e.g. close to the more precise representation) may not be noticeable in the periphery. In accordance with some embodiments, reducing the precision of the representation may advantageously save memory, network, and/or compute bandwidth and may provide power savings.

[0150] Some embodiments may be implemented for both wired and wireless applications (e.g. wireless VR). Wireless applications may particularly benefit from compression of the color representation. For example, the screen may be compressed away from the center (or area of focus). Using less bits in the color representation may improve network speed. By using full precision may in the focus region, some embodiments efficiently dedicate encoding resources on a region of the screen that matters most to the user. For example, the focus region may be assumed to be the center of screen (e.g. static). The focus region may also change dynamically based on other factors such as motion information (e.g. from a VR headset), motion prediction, content (e.g. motion in the scene), etc. But a better user experience may be provided with eye tracking/gaze tracking to identify the focus region.

[0151] In one example of reducing precision, a mask may be applied which is based on color perception. A mask may be developed based on study of human visual preferences. For example, a mask may have a number of regions and each of the regions may be different for different colors. Additional screen region outside of mask region may be compressed at same value as outer most mask region, or further degraded.

[0152] Turning now to FIGS. 6E to 6J, embodiments of color masks may be represented by any of a variety of two or more successively surrounded, non-intersected regions. While the regions illustrated together, a mask for each may be defined and applied separately. The masks may have any shape such as circular (e.g. FIGS. 6E and 6G), elliptical (e.g. FIGS. 6F, 6G, and 6H), square or rectangular (e.g. FIG. 6I), or arbitrary (e.g. FIG. 6J). The inner most region is generally uncompressed (e.g. 0% compression), but may have compression applied in some use cases (e.g. a power saving setting, see FIG. 6J with 10% compression). The inner most region may be surrounded by one or more successive, non-intersecting regions with successively more compression applied for each successive region (e.g. further away from the focus area). The regions may have a common center (e.g. FIGS. 6E and 6F) or no common center (e.g. FIGS. 6H and 6J). The orientation of the masks may be aligned with the display (e.g. FIGS. 6E, 6F, 6G, and 6I) or not (e.g. FIGS. 6H and 6J). The shape of each region may be the same (e.g. FIGS. 6E, 6F, and 6H) or may be different from each other (e.g. FIGS. 6G, 6I, and 6J).

[0153] Turning now to FIGS. 6K and 6L, an embodiment of a color mask 650 may be applied to an image area 652 based on a focus area. For example, if the focus area is roughly centered (e.g. if static if that is where the user is looking), the color mask may also be roughly centered when applied to the image area (e.g. see FIG. 6K). If the focus area moves (e.g. based on gaze information, motion information, content, etc.), the color mask may likewise move based on the new focus area (e.g. see FIG. 6L).

[0154] In another example of reducing precision, a formula may be applied based on the location of the target pixel relative to the focus region. For example, the system may calculate the shortest distance from the target pixel to the focus region boundary and reduce the precision proportionally to the calculated distance. Alternatively, a particular pixel may be selected as the focal point (e.g. a focal pixel) and the distance may be calculated from the target pixel to the focal pixel. The system may use a linear formula, a non-linear formula (e.g. parabolic), or other suitable formula for the proportional precision reduction. The system may also maintain a set of ranges for the precision reduction (e.g. 0 to 100 pixels [no reduction]; 101 to 300 pixels [20% reduction]; 301 pixels or more [50% reduction]).

[0155] In some embodiments, an average may be selected, or the user may select from a set of pre-determined masks to decide which color perception they like best. For example, some people may be more sensitive to red, but not so much to blue. Some people may be color blind. In some embodiments, there may be a calibration per user. For example, a calibration may provide precise user color perception. or average. Generally, eye trackers involve some user calibration. Color calibration may be done at same time as eye tracker calibration. The calibration may be based on, for example, a just noticeable difference (JND). During a calibration phase, the user may be asked to focus on an area and give a response when they notice a color change in the periphery. Or the user may be asked if two colors appear the same on the periphery, when in fact there is some difference between the colors (e.g. to determine how much variation is perceived by the user). In some embodiments, the calibration or other settings (e.g. amount of compression in various regions may be user adjustable (e.g. setting/slider bar for more compression/less compression) or included as part of various power/performance settings.

[0156] The human eye may be sensitive to motion on the periphery. The user may not recognize an object immediately but they may notice the motion. Then the motion may direct the user’s gaze towards the motion. Preferably there is no sharp drop-off from one region to the next. In the focus region, for example, the color may be uncompressed. In the next region if the color is 50% compressed, the change may be too noticeable. Gradual degradation may be preferred so the boundaries are less discrete (e.g. 0% to 25% to 50%, etc.). For example, some displays may be higher pixel density (e.g. a 4K display) and flicker may lead to motion sickness or an otherwise unfavorable user experience. In some embodiments, gradual degradation may also reduce perceptible flicker from one region to the next.

[0157] When sending information from a GPU to a VR system or a display, there is a transmit phase. Some embodiments may encode before transmit. Many HMDs have cable interface, so it may be a wired or wireless transmit. In accordance with some embodiments, the system can also apply filters such a blurring filter. For example, the color mask may be implemented as a pixel shader which is applied to the stream. Once the frame buffer is rendered, the system may post-process the frame buffer to degrade the pixel values so that when the buffer is transmitted the amount of data to transmit is reduced. For example, the pipeline may include a filter to degrade the color before encoding. In accordance with some embodiments, the user may have substantially the same perception of performance (e.g. little or no perceptible loss of detail) while gaining network performance, memory savings, and/or power savings. Higher performance systems (e.g. rendering at 90 frames-per-second (fps) on 4K screens) may realize even more savings.

[0158] Turning now to FIG. 6M, an embodiment of an electronic processing system 660 may include a color compressor 662 implemented as a specialized HW unit. For example, a GPU 664 may prepare image information in a frame buffer 666. The color compressor 662 may retrieve gaze information from a gaze tracker 668 and color maps from a color map store 670 to compress color data of the image information in the frame buffer 665. The color compressor 662 may produce a color corrected frame buffer 672 (e.g. which has less bits as compared to frame buffer 665 even if stored in the same memory area) which may be transmitted to a HMD 674.

[0159] In addition, or alternatively, aspects may be implemented in a GPU or an API call. For example, an API call could send work to the GPU. If there is a specialized HW unit, e.g. a HW encode/decode unit, the work could be offloaded. The frame buffer may be provided the HW unit for encode into H.264, for example, and the HW unit can degrade the color information in accordance with the mask before the encode. For example, the HW unit may directly receive the gaze information or may receive it from the API call. The color masks may be loaded on the HW unit. On a per pixel basis, RGB may be input separately. For example, the color map store 670 may have a red color mask 676, a green color mask 678, and a blue color mask 680 (e.g. which may all be different from each other). Some embodiments may sample based on pixel position against the loaded color mask and process accordingly. The output of processing the color mask may be a color adjusted frame buffer (e.g. with reduced color precision in accordance with the color mask). Additional compression may then be applied to transmit even less bits.

[0160] Some embodiments may provide benefits for streaming video content (e.g. YOUTUBE content). For example, a 360 degree videos may stream directly from the cloud to a local machine. A second worth of data may be pre-cached before the video starts playing back. In accordance with some embodiments, encoding may be performed on the fly. While there may be some latency in sending the data, the whole, uncompressed full resolution image does not need to be sent down to cell phone or head mounted display. Some embodiments may use a focus region or what the user is looking at to compress the color information in the image. With a 5G network, for example, performance may be about 1 ms end-to-end delay. So if the servers are relatively close, some embodiments may predict where the user’s eye will be next frame and use that information for focus-based color compression. For example, at 90 fps the frame period is about 12 ms and the system may estimate where the focus region will be 12 ms later. Advantageously, using focused-based color compression may provide network, memory, and/or power savings on the cloud side.

[0161] Prioritized Viewport Renderer and Resizer

[0162] Turning now to FIG. 7A, an embodiment of an electronic processing system 700 may include an application processor 711, persistent storage media 712 communicatively coupled to the application processor 711, and a parallel processing unit (PPU) 713 communicatively coupled to the persistent storage media 712 and the application processor 711. The PPU 713 may include an image compressor apparatus 714 as described herein (e.g. see FIG. 7B-7H).

[0163] Turning now to FIG. 7B, an embodiment of a graphics viewport apparatus 720 may include a frame divider 721 to divide a frame into two or more viewports, a viewport prioritizer 722 communicatively coupled to the frame divider 721 to prioritize the two or more viewports, a renderer 723 communicatively coupled to the viewport prioritizer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter 724 communicatively coupled to the renderer 723 to transmit a completed rendered viewport, wherein the renderer 723 is further to render another viewport of the frame at a same time as the viewport transmitter 724 transmits the completed rendered viewport. The frame divider 721 may dynamically re-divide the frame into a new set of two or more viewports. For example, the frame divider 721 may dynamically re-divide the frame into the new set of two or more viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information, content information, and/or an optical property of a target head mounted display.

[0164] In some embodiments, the viewport prioritizer 722 may dynamically prioritize the two or more viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information, content information, and/or an optical property of a target head mounted display. Some embodiments of the apparatus 720 may further include a multi-view encoder 725 communicatively coupled to the renderer 723 to encode the two or more viewports. The viewports may have different performance settings corresponding the assigned priorities. For example, higher priority viewports may be rendered with higher performance (e.g. higher resolution, higher frame rate) while lower priority viewports may be rendered with lower performance. Advantageously, some embodiments may improve one or more of processing bandwidth, memory bandwidth, network bandwidth, and/or power consumption.

[0165] The apparatus 720 may also include a motion detector to detect motion of a real object, a motion predictor communicatively coupled to the motion detector to predict a motion of the real object, and an object placer communicatively coupled to the motion detector and the motion predictor to place a virtual object relative to the real object based on the predicted motion of the real object viewport (e.g. as described in more detail in connection with FIGS. 9A to 9D, 10A, and 10B below).

[0166] Embodiments of each of the above application processor 711, persistent storage media 712, PPU 713, graphics viewport apparatus 714/720, frame divider 721, viewport prioritizer 722, renderer 723, viewport transmitter 724, multi-view encoder 725, and other components may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic such as, for example, programmable logic arrays (PLAs), FPGAs, complex programmable logic devices (CPLDs), or in fixed-functionality logic hardware using circuit technology such as, for example, ASIC, complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof. Alternatively, or additionally, these components may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more operating system applicable/appropriate programming languages, including an object-oriented programming language such as JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.

[0167] For example, the system 700 may include similar components and/or features as system 100, further configured to dynamically resize and assign priorities to viewports and transmit rendered viewports as they are ready (e.g. while other viewports render). For example, the PPU 713 may include similar components and/or features as the parallel processor 200, further configured with a graphics viewport apparatus as described herein. The system 700 may also be adapted to work with a stereo head mounted system such as, for example, the system described in connection with FIGS. 11-15 below. In particular, the HMII 1100 described in more detail below may include a gaze tracker to provide gaze/focus information to the frame divider 721 and/or viewport prioritizer 722.

[0168] Turning now to FIG. 7C, an embodiment of a method 730 of processing a frame may include dividing the frame into two or more viewports at block 732, prioritizing the two or more viewports at block 734, rendering a viewport of the frame in order in accordance with the viewport priorities at block 736, transmitting a completed rendered viewport at block 738, and rendering another viewport of the frame at a same time as transmitting the completed rendered viewport at block 740. In some embodiments, the method 730 may include dynamically re-dividing the frame into a new set of two or more viewports at block 742. For example, the method 730 may include dynamically re-dividing the frame into the new set of two or more viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information, content information, and/or an optical property of a target head mounted display at block 744. In some embodiments, the method 730 may include dynamically prioritizing the two or more viewports at block 746. For example, the method 730 may include dynamically prioritizing the two or more viewports based on one or more of an area of focus, gaze information, motion information, motion prediction information, content information, and/or an optical property of a target head mounted display at block 748.

[0169] Embodiments of the method 730 may be implemented in a system, apparatus, GPU, PPU, or a graphics processor pipeline apparatus such as, for example, those described herein. More particularly, hardware implementations of the method 730 may include configurable logic such as, for example, PLAs, FPGAs, CPLDs, or in fixed-functionality logic hardware using circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or additionally, the method 730 may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more operating system applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. For example, the method 730 may be implemented on a computer readable medium as described in connection with Examples 34 to 38 below.

[0170] For example, embodiments or portions of the method 730 may be implemented in applications (e.g. through an API) or driver software. Other embodiments or portions of the method 730 may be implemented in specialized code (e.g. shaders) to be executed on a GPU. Other embodiments or portions of the method 730 may be implemented in fixed function logic or specialized hardware (e.g. in the GPU). For example, some embodiments may be implemented as a hardware block in the encode and transmit stage of the graphics pipeline.

[0171] Conventionally, transmission of a frame may happen after a full frame is ready for a wireless VR system. Some embodiments may advantageously transmit a prioritized partial frame buffer for wireless VR. For example, some embodiments may implement partial frame buffer prioritized rendering and transfers. Advantageously, some embodiments may start sending a portion of the frame buffer as soon as rendering of that portion of an image is complete and may not wait for a full frame to be ready. For example, some embodiments may include a prioritized region of interest (ROI) for wireless VR use cases and applications, so there is a priority associated with which region of the image is being encoded and decoded. In some embodiments, eye tracking information may be utilized to identify a prioritized ROI. Some embodiments may provide similar benefits for a wired VR system (e.g. where transmission occurs over a cable).

[0172] Turning now to FIG. 7D, a frame 762 may be divided into nine viewports 762a through 762i. Each viewport may be assigned a relative priority. For example, viewport 762e may be assigned priority 1 (e.g. highest priority), viewports 762b and 762h may be assigned priority 2, viewports 762d and 762f may be assigned priority 3, and viewports 762a, 762c, 762g, and 762i may be assigned priority 4 (e.g. lowest priority). In some embodiments, consecutive priorities may be assigned to each viewport (e.g. priorities 1 through 9 for viewports 762a through 762i). In some embodiments, a priority may indicate both a rendering order and a relative rendering performance. For example, priority one may get rendered first with full resolution and/or a highest frame rate while priority 4 may get rendered last with a lower resolution and/or a lower frame rate. Advantageously, some embodiments may improve one or more of processing bandwidth, memory bandwidth, network bandwidth, and/or power consumption.

[0173] In some embodiments, the relative priority and the amount of work to perform for each viewport may be based on the HVS. The pixels towards the periphery are not viewed as much as the pixels in the center. The center pixels get exploded and you see more details. Some embodiments may use the distortion maps to prioritize the portion of the screen which is getting looked at and render those portions first (and in more detail-high resolution).

[0174] Turning now to FIG. 7E, in accordance with some embodiments the size and/or priorities of the viewports 762a through 762i of the frame 762 may be dynamically adjusted. In some embodiments, the number of viewports may also be dynamically adjusted (e.g. six viewports instead of nine). For example, the size of the viewports may be adjusted based on one or more of an area of focus, gaze information, motion information, motion prediction information, content information, or an optical property of a target head mounted display. The priority of the viewports may also be adjusted, for example, based on one or more of an area of focus, gaze information, motion information, motion prediction information, and content information. In one example, the user may be turning their head towards the right and looking above and to the right of the center of the screen. Based on this information, the system may re-divide the frame or re-size the viewports 762a-762i (e.g. as compared to FIG. 7D) and change the priorities of the viewports such that the right edge viewport 762h is larger and has the highest priority, the central viewport 762e is smaller and has the next highest priority. The user may have little attention on the left most viewports 762a to 762c. Advantageously, the system may make these viewports relatively large and assign them the lowest priority to substantially reduce the amount of resources applied to the image data in those viewports (e.g. lower resolution, more compression, lower frame rate, etc.).

[0175] Turning now to FIGS. 7F to 7G, some embodiments may divide the frame into viewports based on an optical characteristic of a target HMD. For example, different HMDs may employ different optics and lenses which may distort the image. The image may be processed to be pre-distorted to account for the lens distortion, so the final image appears undistorted. Some embodiments may load a distortion map for a particular HMD and sub-divide the frame into multiple sections (e.g. viewports) based on the distortion map (e.g. either precisely or an approximation). A priority, resolution, frame rate, etc., for example, may then be assign to each section (or the processing resources may be based on or indicative of the assigned priority). A frame representation 774 may correspond to a screen for a first target HMD and the system may divide the frame 774 into viewports 774a to 774e based on a distortion map corresponding to the optical characteristics of the first target HMD. Another frame representation 776 may correspond to a screen for a second target HMD and the system may divide the frame 776 into viewports 776a to 776e based on a distortion map corresponding to the optical characteristics of the first target HMD. For example, the type of HMD attached to the system may be detected, communicated from the HMD, or the user may select what type of HMD is attached from a pull-down list, after which the system may load the HMD-specific distortion map. Other settings or adjustments may be made, for example, for different applications, for different user preferences, etc., associated with the attached HMD. The distortion map may also be further broken into more sub-sections for finer control (e.g. 10 viewports).

[0176] Turning now to FIG. 7H, some embodiments may advantageously provide partial frame buffer transfers and prioritized rendering. For a frame 778 having five viewports prioritized 1 through 5, the system may render the viewports in the priority order. The system may start sending the first viewport as soon as it is done rendering (e.g. without waiting for the next viewport to render). The same render/send process continues for each of the viewports. The full set of viewports may be merged in the display. For example, encoding may be performed utilizing High Efficiency Video Coding (HEVC) tiles or multi-view HEVC. For subsequent frames, the system may progressively re-prioritize and/or re-size the viewports starting from an identified area of importance. For example, the system may use eye tracker information to identify a portion of the frame to prioritize. The system may also change the priorities based on motion (e.g. if the user is turning their head or body), content (e.g. where the application wants the user to focus such as something more interesting happening that the application wants the user’s attention on), and/or motion prediction (e.g. if the user is turning their head, the system may prioritize a side region which will be coming into view based on the prediction that the user will continue to turn their head in the same direction).

[0177] For example, the system may render the first priority viewport first, at high resolution. The system may then render the second priority viewport next, at medium resolution. The system may then render the remaining prioritized viewports in order, at low resolution. Advantageously, the system may start transmitting the first rendered section while rendering the second section. The receiving unit (e.g. HMD) can start decoding the first section as soon as it is received.

[0178] The priorities may remain static (e.g. if no gaze tracker or motion input). Preferably priorities can be changed dynamically, for example, based on a change in the user’s gaze. Motion in one of the sections, for example, may also be a basis for changing the priority of a viewport. The center area may not always be the first priority. If the user is looking at side or top section, that section may become the first priority. The number of regions, the size of the regions, and the shape of the regions may change. The priorities of the regions may also change. Advantageously, the encode may start happening before the full frame is done rendering.

[0179] In some embodiments, the full frame buffer may not be sent under some circumstances. For example, if differences between the viewport in two frames are small, the system may not resend the viewport. The system may send a signal to re-use the viewport (e.g. or it just may not get redrawn until a new region is sent). The GPU may send chunks of display with the HMD being able to re-assemble those chunks at the HMD. For example, the HMD may only draw the sections it receives. All sections may not be updated for every frame (presumably because they were not needed or were low priority). The communication may be direct from the GPU to the HMD, or through the CPU. For example, some wireless protocols may benefit from CPU communication to the HMD (e.g. for WiFi). In general, the prioritized rendering may be done on the GPU.

[0180] Even for a particular HMD, the system may change the size/configuration of viewports (e.g. based on content). For movies, the periphery may be less important so the system may increase the size of a central viewport. For games, different viewport sizes may be preferred for adventure games versus role-playing games versus first-person shooter games. The viewports may be assigned different characteristics based on averaging, user settings, publisher settings, etc. Advantageously, some embodiment may provide the tile-based transport based on priorities assigned to the viewports and perform encoding while transmitting.

[0181] Advantageously, some embodiments may provide individual rendering frequencies for a wireless VR. Objects in the periphery may not need to be rendered at the same rate as the center of the screen. Some embodiments may render different blocks of an image at different fps for prioritized rendering and display. Advantageously, some embodiments may reduce the amount of work being done or allow doing more work at the center or ROI of the image. For an HMD, this may be an offshoot of using the optical characteristics of the HMD to change rendering (e.g. coarse pixel shading/multi-resolution shading). Some embodiments may blend content at the edges of the different viewports (e.g. blending new data with stale pixel data). For example, a HMD may include sensors to provide eye/gaze tracking information which the GPU/CPU may use to change the ROI dynamically and adjust the viewports. Using FIG. 7H as an example, the rightmost region with priority 1 may be rendered at 120 fps, the central region with priority 2 may be rendered at 60 fps, while the remaining regions with lower priority may be rendered at 30 fps. In general, identifying things that the user cares about or parts of the image that are changing fast may provide a basis to alter the fps of rendering for those regions.

[0182] In accordance with some embodiments, the motion of eye may predict a subsequent motion of head. The system may sometimes de-prioritize a viewport away from the gaze point in the direction of the motion. For example, frame rates for a stable center gaze may be 30-90-30 fps (e.g. with 90 fps at the central viewport). As the gaze point moves to the edge the system may change the frame rates to 10-90-60 (e.g. 60 fps at the viewport where objects/scenes of interest will be entering at the edge and moving to the center). Objects/scenes away from the direction of motion will not be noticed by the user and may be updated less frequently. Some embodiments may also utilize predictive motion. Some embodiments may also dynamically change the viewport sizes so the leading edge is skewed bigger and the center and trailing edge are smaller. For example, some embodiments may change the priority of viewports and can skew the regions based on predicted head motion. In some embodiments, a head motion prediction can be fed into a next frame for decision making. If the head is moving fast, for example, refresh rates may be reduced because not much detail may be noticed (the system may also apply motion blur or other temporal filters).

[0183] For example, a frame budget may be about 16 ms for 60 fps and 12 ms for 90 fps. Some embodiments may adjust the viewport sizes, refresh rates, and other performance parameters to meet the frame budget. In a game or on-the-fly 3D content, the application may know how quickly and where the objects are moving. The application may provide the information to the GPU (e.g. through an API call) to bias refresh rates or other performance parameters for the viewports. Object motion may also be fed into the next frame for decision making (e.g. as to viewport priority, frame rate, size, etc.).

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