Intel Patent | Vision Deficiency Adjusted Graphics Rendering

Patent: Vision Deficiency Adjusted Graphics Rendering

Publication Number: 20190042698

Publication Date: 2019-02-07

Applicants: Intel

Abstract

An embodiment of a graphics apparatus may include a vision characterizer to determine a vision characteristic associated with a user, and a parameter adjuster communicatively coupled to the vision characterizer to adjust a render parameter of a graphics system based on the determined vision characteristic. Other embodiments are disclosed and claimed.

TECHNICAL FIELD

[0001] Embodiments generally relate to data processing and to graphics processing via a graphics processing unit. More particularly, embodiments relate to vision deficiency adjusted graphics rendering.

BACKGROUND

[0002] Parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Graphics processors may use fixed function computational units to process graphics data. Graphics processors may also use programmable units, enabling such processors to support a wider variety of operations for processing vertex and fragment data. Various settings, parameters, and configurations may be applied to operations on graphics data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:

[0004] FIG. 1 is a block diagram of an example of an electronic processing system according to an embodiment;

[0005] FIG. 2 is a block diagram of an example of a graphics apparatus according to an embodiment;

[0006] FIGS. 3A to 3B are flowcharts of an example of a method of adjusting a graphics parameter according to an embodiment;

[0007] FIG. 4 is an illustrative diagram of a head mounted display (HMD) showing an eye chart for the left eye;

[0008] FIG. 5 is an illustrative diagram of a HMD showing an eye chart for the right eye;

[0009] FIG. 6 is an illustrative diagram of a HMD showing a color perception test;

[0010] FIG. 7 is an illustrative diagram of a HMD showing a depth perception test;

[0011] FIG. 8 is an illustration of an example of a head mounted display (HMD) system according to an embodiment;

[0012] FIG. 9 is a block diagram of an example of the functional components included in the HMD system of FIG. 8 according to an embodiment;

[0013] FIG. 10 is a block diagram of an example of a general processing cluster included in a parallel processing unit according to an embodiment;

[0014] FIG. 11 is a conceptual illustration of an example of a graphics processing pipeline that may be implemented within a parallel processing unit, according to an embodiment;

[0015] FIG. 12 is a block diagram of an example of a streaming multi-processor according to an embodiment;

[0016] FIGS. 13-15 are block diagrams of an example of an overview of a data processing system according to an embodiment;

[0017] FIG. 16 is a block diagram of an example of a graphics processing engine according to an embodiment;

[0018] FIGS. 17-19 are block diagrams of examples of execution units according to an embodiment;

[0019] FIG. 20 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0020] FIGS. 21A-21B are block diagrams of examples of graphics pipeline programming according to an embodiment;

[0021] FIG. 22 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0022] FIG. 23 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0023] FIG. 24 is a block diagram of an example of a system on a chip integrated circuit according to an embodiment.

DESCRIPTION OF EMBODIMENTS

[0024] Turning now to FIG. 1, an embodiment of an electronic processing system 10 may include a graphics processor 11, memory 12 communicatively coupled to the graphics processor 11, a render subsystem 13 communicatively coupled to the graphics processor 11, and a parameter adjuster 14 communicatively coupled to the render subsystem 13 to adjust a render parameter of the render subsystem 13 based on a vision profile associated with a user. In some embodiments, the system 10 may further include a vision profile developer 15 communicatively coupled to the parameter adjuster 14 to develop the vision profile associated with the user. For example, the vision profile developer 15 may be configured to test a vision of the user to develop the vision profile. Additionally, or alternatively, the vision profile developer 15 may also be configured to identify the user, and load a vision profile associated with the identified user. The vision profile may include, for example, information related to one or more of visual acuity, color perception, depth perception, etc. The render parameter may include, for example, one or more of a level of detail parameter, a resolution parameter, a color precision parameter, a stereo render parameter, etc.

[0025] For a graphics system, various settings and/or parameters may affect how images are processed and displayed, and the corresponding memory, processing bandwidth, network bandwidth, and power consumption of the system based on those settings/parameters. High level parameters may include resolution (e.g., extended graphics array (XGA) resolution of 1024.times.768 pixels; full high definition (HD) resolution of 1920.times.1080 pixels; ultra HD (UHD) resolution of 3840.times.2160 pixels, 4K resolution of 4096.times.2160 pixels, etc.), frame rate (e.g., 24 frames per second (fps), 30 fps, 60 fps, 90 fps, etc.), color depth (e.g., 8-bit color precision, 16-bit color precision, 24-bit color precision, etc.), etc. Lower level parameters may include a variety of GPU parameters. These GPU parameters include GPU/CPU/ring frequency, power distributions (how much power to provide various components), cache configurations (how much cache to allocate to certain types of resources), dispatch width for various dispatch shaders, shader resolution, multi-sampling anti-aliasing (MSAA) depth, tessellation quality, etc. Other parameters may include model complexity, coarse pixel size, etc. Depending on the particular embodiment, any of a number of parameters may be suitable for adjustment based on the vision profile associated with the user.

[0026] Embodiments of each of the above graphics processor 11, memory 12, render subsystem 13, parameter adjuster 14, vision profile developer 15, and other system components may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), or fixed-functionality logic hardware using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

[0027] Alternatively, or additionally, all or portions of these components may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more operating system (OS) applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. For example, the memory 12, persistent storage media, or other system memory may store a set of instructions which when executed by the graphics processor 11 cause the system 10 to implement one or more components, features, or aspects of the system 10 (e.g., the parameter adjuster 14, the vision profile developer 15, etc.).

[0028] For example, the system 10 may include similar components and/or features as the processing system 1600, the data processing system 2500, and/or the system-on-a-chip (SoC) integrated circuit 2700 (each described in more detail below), further configured to adjust a render parameter of the associated graphics system based on a vision profile associated with a user. For example, the graphics processor 11 may include similar components and/or features as the processor system 1204, the general processing cluster (GPC) 1300, the graphics pipeline 1400, the streaming multi-processor (SM) 1500, processor 1700, graphics processor 1800, graphics processing engine 1900, graphics processor 2000, thread execution logic 2100, and/or graphics processor 2300 (each described in more detail below), further configured with a parameter adjuster as described herein. The system 10 may also be adapted to work with a stereo head mounted system such as, for example, the HMD system 1100 described in connection with FIG. 8 below. In particular, the HMD system 1100 described in more detail below may include a gaze tracker and/or eye camera to provide user/vision information to the vision profile developer 15.

[0029] Turning now to FIG. 2, an embodiment of a graphics apparatus 20 may include a vision characterizer 21 to determine a vision characteristic associated with a user, and a parameter adjuster 22 communicatively coupled to the vision characterizer 21 to adjust a render parameter of a graphics system based on the determined vision characteristic. Some embodiments of the apparatus 20 may further include a vision profile developer 23 communicatively coupled to the vision characterizer 21 to develop a vision profile associated with the user. For example, the vision profile developer 23 may be configured to test the vision of the user to develop the vision profile. Additionally, or alternatively, the vision profile developer 23 may also be configured to identify the user, and load a vision profile associated with the identified user. The vision profile may include information related to one or more of visual acuity, color perception, depth perception, etc. The render parameter may include one or more of a level of detail parameter, a resolution parameter, a color precision parameter, a stereo render parameter, etc.

[0030] Embodiments of each of the above vision characterizer 21, parameter adjuster 22, vision profile developer 23, and other components of the apparatus 20 may be implemented in hardware, software, or any combination thereof. For example, hardware implementations may include configurable logic such as, for example, PLAs, FPGAs, CPLDs, or fixed-functionality logic hardware using circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or additionally, these components may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more OS applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.

[0031] Turning now to FIGS. 3A to 3B, an embodiment of a method 30 of adjusting a graphics parameter may include determining a vision characteristic associated with a user at block 31, and adjusting a render parameter of a graphics system based on the determined vision characteristic at block 32. In some embodiments, the method 30 may further include developing a vision profile associated with the user at block 33. For example, some embodiments may include testing the vision of the user to develop the vision profile at block 34. Some embodiments may additionally, or alternatively, include identifying the user at block 35, and loading a vision profile associated with the identified user at block 36. For example, the vision profile may include information related to one or more of visual acuity, color perception, and depth perception at block 37. For example, the render parameter may include one or more of a level of detail parameter, a resolution parameter, a color precision parameter, and a stereo render parameter at block 38.

[0032] Embodiments of the method 30 may be implemented in a system, apparatus, computer, device, etc., for example, such as those described herein. More particularly, hardware implementations of the method 30 may include configurable logic such as, for example, PLAs, FPGAs, CPLDs, or in fixed-functionality logic hardware using circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or additionally, the method 30 may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more OS applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. For example, the method 30 may be implemented on a computer readable medium as described in connection with Examples 19 to 24 below.

[0033] For example, embodiments or portions of the method 30 may be implemented in applications (e.g., through an application programming interface (API)) or driver software running on an operating system (OS). Other embodiments or portions of the method 30 may be implemented in specialized code (e.g., shaders) to be executed on a graphics processor unit (GPU). Other embodiments or portions of the method 30 may be implemented in fixed function logic or specialized hardware (e.g., in the GPU).

[0034] Many people do not have perfect vision. To overcome that, people may wear glasses. However, when using virtual reality HMDs not of all the devices support wearing glasses under them. For example, GOOGLE CARDBOARD and SAMSUNG GEAR VR may have no extra space for glasses inside the HMD. Even if the user is wearing glasses or contact lenses, a person’s prescription may change over time such that even with corrective lenses the user’s visual acuity may have some deficiency. Even if the user has good visual acuity, the user may have some other vision deficiency. Some virtual reality (VR) systems may include lower performance processors, where fast rendering performance for a smooth VR experience is more difficult to achieve. People with vision deficiencies might not be able to see all the details rendered. Nevertheless, conventional systems which provide the HMD with the frame buffer will render at the same quality and performance cost without taking a user’s vision deficiencies into account. Advantageously, some embodiments may provide rendering improvements or optimizations for user-specific visual acuity, colorblindness, depth perception, and/or other visual deficiencies (e.g., eye inclusions, blindness, night vision, etc.). Various embodiments may improve the performance and/or reduce the power consumption of a VR system, an augmented reality (AR) system, a mixed reality system, merged reality system, or other graphics/display system.

[0035] In some embodiments, performance may be improved by adjusting the rendering based on one or more of a user’s visual acuity, a user’s color perception, and a user’s depth perception. A large percentage of the population may have a visual acuity deficiency. A significant percentage of the population may have a color perception deficiency. For example, 8% of the male and 0.6% of the female population may be colorblind. A significant percentage of the population may have a depth perception deficiency. For example, according to a British study, 12% of the population may not see in three dimensions (3D).

[0036] In some embodiments, the user may enter or provide their own vision profile. For example, a graphical user interface may guide the user through a series of questions, prompts, menus, pull-downs, buttons, boxes, etc. to enter their vision information. For example, the user may be asked to enter their visual acuity (e.g., prompted with “What were the results of your last vision exam? Left Eye: 20/XX; Right Eye: 20/YY”), to identify any known colorblindness (e.g., prompted with “Do you have any color perception issues [check all that apply]? [ ] Red/Green Colorblind; [ ] Deuteranopia sight; [ ] Tritanopia sight; [ ] Monochromatic sight; etc.”), and to identify any depth perception issues (e.g., prompted with “Can you see in 3D? Y/N”). The user’s responses may be stored as a vision profile for the user. In some embodiments, additionally or alternatively, the results of a professional eye examination may be saved in a vision profile and uploaded to a cloud-based storage service (e.g., for later download by the user or by a graphics systems utilized by the user).

[0037] For example, the user may be identified by name, address, a selected username, a unique identification number, etc. and the vision profile may be stored in association with the user identification. Biometric user identification may also be used to identify the user. For example, a HMD system may include iris identification technology to identify a user. Some embodiments may include facial recognition technology to identify the user. In some embodiments, the user’s devices may additionally or alternatively be used to identify the user. For example, the user may sign on to a system with an associated username. The user may carry a device with a unique radio signature. For example, the user may have a smartphone device with a BLUETOOTH or WIFI radio which broadcasts a unique identification signal. The vision profile information may be stored in a file (e.g., encrypted and/or editable by the user), in a database, or in some other data structure which is readable by the graphics systems. The vision profile information may be stored on a host system, on a graphics display system (e.g., a HMD), on a cloud service, etc. When the user has been identified, the associated vision profile information may be loaded from wherever it may be stored, and appropriate adjustments may be made to the graphics system based on the user’s vision deficiencies identified in the loaded vision profile.

[0038] Some embodiments may perform an eye exam of the user inside the HMD. For example, the user may be prompted to go through an interactive eye exam inside a VR headset. In some embodiments, the exam(s) may be similar to exam(s) given at a vision center. Various tests may determine if the user has any relevant deficiencies in their vision (e.g., deficiencies that may affect how the user perceives the displayed graphics). If a vision deficiency is found, the system may adapt various rendering techniques to gain better performance and/or to reduce power consumption. Advantageously, adjusting the render process based on the human vision properties associated with a specific user may speed-up rendering performance and/or save power consumption in a HMD without negatively impacting the perceived image quality. The vision profile information associated with the user may be created or updated based on the results of the exam. The exam may be a one-time setup process per user, or may be repeated periodically and/or at the request of the user. The exam may also be updated for a change in the device. For example, readability might be limited by the screen of the HMD, so the tests may be repeated if a newer version of the HMD is used (e.g., with a higher resolution screen). Visual perception may also be different for each different device the user utilizes, so the test may be updated for each of the user’s devices.

[0039] Turning now to FIGS. 4 to 5, an example of a visual acuity test may include a 20/20 vision test. An embodiment of a HMD 42 may include a left eye display 43 and a right eye display 44. In the 20/20 vision test, the visual acuity of the user can be determined per eye. For example, an eye chart 52 may be displayed for the left eye on the left eye display 43 (FIG. 4) to test the left eye acuity, and separately on the right eye display 44 (FIG. 5) to test the right eye acuity. The user may be prompted to type the letters corresponding to the lowest line on the eye chart that they can read. A result of the test may determine, for example, that the user can see compared to the average human only 20% on the left eye, and about 75% on the right eye (e.g., or that the user has 20/60 vision in one eye and 20/100 vision in the other eye). Based on the determined lower visual acuity, the system may adjust rendering to a much lower rendering resolution on the left eye, and a bit lower resolution on the right eye. Frame rate, color depth, and/or other properties or parameters corresponding to various levels of detail of the graphics may be adjusted as well.

[0040] In some embodiments, the HMD may include a camera or device to automatically determine the visual acuity of the user. For example, the HMD may include an eye tracker or iris identification technology which may include a camera that can take a picture of the eye. Some embodiments may include an autorefractor to automatically determine the user’s visual acuity (e.g. without prompts or manual entries by the user). For example, an autorefractor may provide an objective measurement of the user’s refractive error (e.g. to determine the prescription of corrective lenses for the user). The autorefractor may measure how light is changed as it enters the user’s eye. For example, a camera or sensor may detect the reflections from a cone of infrared light. The reflections may be used to determine the size and shape of a ring in the retina at the back of the eye. By measuring the ring, the autorefractor may determine when the user’s eye properly focuses an image. In some embodiments, the autorefractor may change a magnification until the image comes into focus. The process may be repeated in at least three meridians of the eye, from which the autorefractor may calculate the refraction of the eye, sphere, cylinder and axis. The information determined by the autorefractor may be stored in the vision profile information associated with the user.

[0041] If the determined visual acuity is less than a threshold value, some embodiments may render at lower resolution (e.g., as compared to its current resolution). In addition, or alternatively, if the visual acuity is greater than the threshold value, some embodiments may render at higher resolution (e.g., as compared to its current resolution). Some embodiments may support a range of threshold values or a tier of threshold values. For example, some embodiments may determine if the visual acuity is less than a first threshold value and greater than a second threshold value and adjust the rendered resolution accordingly. Some embodiments may adjust performance parameters in addition to, or alternative to, the render resolution. For example, if the user is determined to have reduced visual acuity a low polygon model may be used instead of a high polygon model. Workload may advantageously be reduced because there are less vertices and normals to process. The workload may additionally, or alternatively, be adjusted by change a shading rate. For example, if the user’s visual acuity is low, the system may change how the system processes edge thresholds or other performance parameters (e.g., for lower quality results). The adjusted performance parameters may be user-specific (e.g., based on a setup process and/or based on user calibration).

[0042] Turning now to FIG. 6, an example of a color perception test may include a colorblindness test. Any of a variety of tests may indicate the user’s perception of different colors. In the example of FIG. 6, an image 62 may include a number of different colored circles. A user with typical color perception may perceive a number with the image 62 while a user with colorblindness might not perceive the number. If the user is determined to have red/green colorblindness, for example, the rendering may be adjusted to perform a single calculation for those colors in various shaders instead of separate calculations for red and green color channels in the shaders. If the user is determined to have monochromic sight, for example, the rendering may be adjusted to combine otherwise separate red/green/blue color specific calculations into one calculation. In some embodiments, a shader compiler may automatically optimize a shader based on the user’s color perception profile information. In the case when red and green colorblindness is indicated, for example, the shader compiler may automatically find calculations in the shader to skip or simplify (e.g., because seeing red may substantially equal seeing green to the user).

[0043] Some embodiments may advantageously change color encoding for rendering based on the user’s color perception. For example, some embodiments may use color perception of the human visual system (HVS) to change encoding and compress color information in the frame buffer. The quality may change based on color perception. Some embodiments may advantageously save network bandwidth and power, which may be particularly useful for wireless virtual reality (VR) and encode. Some embodiments may provide a simple adjustment to the rendering to reduce color precision required for color representation. For example, some embodiments may use color compression for colors that aren’t well perceived by the user.

[0044] At a high level, some embodiments may use color perception information from the HVS to change the traits of the color representation based on information from a vision profile of the user. For example, color may be represented by 16-bit, 32-bit, etc. But the image/display does not need full precision if the user is not going to notice the difference in the color because they cannot perceive it. The user may perceive a color as red, but whether its maroon or scarlet or something else (e.g., close to the more precise representation) may not be noticeable by some users. In accordance with some embodiments, reducing the precision of the representation may advantageously save memory, network, and/or compute bandwidth and may provide power savings.

[0045] Some embodiments may be implemented for both wired and wireless applications (e.g., wireless VR). Wireless applications may particularly benefit from compression of the color representation. Using less bits in the color representation may improve network speed. In some embodiments, an average may be selected, or the user may select from a set of pre-determined images to decide which color perception they like best. For example, some people may be more sensitive to red, but not so much to blue. Some people may be colorblind. In some embodiments, there may be a calibration per user. For example, a calibration may provide precise user color perception. Generally, HMDs with eye trackers may involve some user calibration. Color calibration may be done at the same time as eye tracker calibration. The calibration may be based on, for example, a just noticeable difference (JND). During a calibration phase, the user may be asked to give a response when they notice a color change. Or the user may be asked if two colors appear the same, when in fact there is some difference between the colors (e.g., to determine how much variation is perceived by the user). In some embodiments, the calibration or other settings/parameters (e.g., amount of compression) may be user adjustable (e.g., setting/slider bar for more compression/less compression) or included as part of various power/performance settings.

[0046] When sending information from a GPU to a VR system or a display, there is a transmit phase. Some embodiments may encode before transmit. Many HMDs have cable interface, so it may be a wired or wireless transmit. In accordance with some embodiments, the system can also apply filters such a blurring filter. For example, the color compression may be implemented as a pixel shader which is applied to the stream. Once the frame buffer is rendered, the system may post-process the frame buffer to degrade the pixel values so that when the buffer is transmitted the amount of data to transmit is reduced. For example, the pipeline may include a filter to degrade the color before encoding. In accordance with some embodiments, the user may have substantially the same perception of performance (e.g., little or no perceptible loss of detail) while gaining network performance, memory savings, and/or power savings. Higher performance systems (e.g., rendering at 90 frames-per-second (fps) on 4K screens) may realize even more savings.

[0047] In some embodiments, a color compressor may be implemented as a specialized HW unit. For example, a GPU may prepare image information in a frame buffer. The color compressor may retrieve color perception information from a vision profile and load corresponding color maps from a color map store to compress color data of the image information in the frame buffer. The color compressor may produce a color corrected frame buffer (e.g., which has less bits as compared to the original frame buffer even if stored in the same memory area) which may be transmitted to a HMD.

[0048] In addition, or alternatively, aspects may be implemented in a GPU or an API call. For example, an API call may send work to the GPU. If there is a specialized HW unit, e.g., a HW encode/decode unit, the work may be offloaded. The frame buffer may be provided the HW unit for encode into H.264, for example, and the HW unit may degrade the color information in accordance with the color maps before the encode. For example, the HW unit may directly receive the vision profile information or may receive it from the API call. The color perception profile may be loaded on the HW unit. On a per pixel basis, RGB may be input separately. For example, the color map store may have a red color map, a green color map, and a blue color map (e.g., which may all be different from each other). Some embodiments may sample based on pixel position against the loaded color map and process accordingly. The output of processing the color maps may be a color adjusted frame buffer (e.g., with reduced color precision in accordance with the color maps). Additional compression may then be applied to transmit even less bits.

[0049] Some embodiments may provide benefits for streaming video content (e.g., YOUTUBE content). For example, a 360 degree video may stream directly from the cloud to a local machine. A second’s worth of data may be pre-cached before the video starts playing back. In accordance with some embodiments, encoding may be performed on the fly. While there may be some latency in sending the data, the whole, uncompressed full resolution image does not need to be sent down to cell phone or head mounted display. Some embodiments may use a color perception profile to compress the color information in the image. Advantageously, using perception-based color compression may provide network, memory, and/or power savings on the cloud side.

[0050] Turning now to FIG. 7, an example of a depth perception test may include a stereo vision test. In the example, of FIG. 7, an image 72 may include a variety of circles arranged in a diamond pattern. A user with typical stereoscopic vision may perceive some of the circles with 3D qualities while a user with a depth perception deficiency may not perceive the 3D qualities. The user may be prompted to identify which, if any, circles appear to have 3D qualities. Because HMDs may provide a stereoscopic view from the left and right eye rendered images, other tests may be made to determine if the user is able to see stereoscopically. For example, in a pre-determined image certain elements may be intended to pop out in 3D. Without 3D vision, those elements may appear flat in the image. The user may be prompted to identify which elements appear to have depth or 3D qualities. If the user is determined to not perceive stereo vision, for example, the rendering may be adjusted to be monoscopic, advantageously saving about 50% of the rendering work load.

[0051] In some embodiments, the results of the various HMD eye exams may be stored in a user profile (e.g., in STEAM or OCULUS HOME) and may be accessed by other VR apps and games to make rendering improvements or optimizations. Some embodiments may increase the demand for VR, AR, mixed, and/or merged reality applications by lowering the required performance for people using these devices without glasses and/or not having perfect vision. While many of the above embodiments relate to GPU operations that are rasterization based, some embodiments may similarly apply to other rendering techniques. For example, embodiments of other rendering algorithms like ray tracing, voxel ray tracing, point rendering, etc., may be configured to adjust a parameter of the rendering based on a vision profile associated with a user. These embodiments may run on a programmable GPU, a CPU, and/or a dedicated processor for that rendering task.

[0052] Head-Mounted Integrated Interface System Overview

[0053] FIG. 8 shows a head mounted display (HMD) system 1100 that is being worn by a user while experiencing an immersive environment such as, for example, a virtual reality (VR) environment, an augmented reality (AR) environment, a multi-player three-dimensional (3D) game, and so forth. In the illustrated example, one or more straps 1120 hold a frame 1102 of the HMD system 1100 in front of the eyes of the user. Accordingly, a left-eye display 1104 may be positioned to be viewed by the left eye of the user and a right-eye display 1106 may be positioned to be viewed by the right eye of the user. The left-eye display 1104 and the right-eye display 1106 may alternatively be integrated into a single display in certain examples such as, for example, a smart phone being worn by the user. In the case of AR, the displays 1104, 1106 may be view-through displays that permit the user to view the physical surroundings, with other rendered content (e.g., virtual characters, informational annotations, heads up display/HUD) being presented on top a live feed of the physical surroundings.

[0054] In one example, the frame 1102 includes a left look-down camera 1108 to capture images from an area generally in front of the user and beneath the left eye (e.g., left hand gestures). Additionally, a right look-down camera 1110 may capture images from an area generally in front of the user and beneath the right eye (e.g., right hand gestures). The illustrated frame 1102 also includes a left look-front camera 1112 and a right look-front camera 1114 to capture images in front of the left and right eyes, respectively, of the user. The frame 1102 may also include a left look-side camera 1116 to capture images from an area to the left of the user and a right look-side camera 1118 to capture images from an area to the right of the user.

[0055] The images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118, which may have overlapping fields of view, may be used to detect gestures made by the user as well as to analyze and/or reproduce the external environment on the displays 1104, 1106. In one example, the detected gestures are used by a graphics processing architecture (e.g., internal and/or external) to render and/or control a virtual representation of the user in a 3D game. Indeed, the overlapping fields of view may enable the capture of gestures made by other individuals (e.g., in a multi-player game), where the gestures of other individuals may be further used to render/control the immersive experience. The overlapping fields of view may also enable the HMD system 1100 to automatically detect obstructions or other hazards near the user. Such an approach may be particularly advantageous in advanced driver assistance system (ADAS) applications.

[0056] In one example, providing the left look-down camera 1108 and the right look-down camera 1110 with overlapping fields of view provides a stereoscopic view having an increased resolution. The increased resolution may in turn enable very similar user movements to be distinguished from one another (e.g., at sub-millimeter accuracy). The result may be an enhanced performance of the HMD system 1100 with respect to reliability. Indeed, the illustrated solution may be useful in a wide variety of applications such as, for example, coloring information in AR settings, exchanging virtual tools/devices between users in a multi-user environment, rendering virtual items (e.g., weapons, swords, staffs), and so forth. Gestures of other objects, limbs and/or body parts may also be detected and used to render/control the virtual environment. For example, myelographic signals, electroencephalographic signals, eye tracking, breathing or puffing, hand motions, etc., may be tracked in real-time, whether from the wearer or another individual in a shared environment. The images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118, may also serve as contextual input. For example, it might be determined that the user is indicating a particular word to edit or key to press in a word processing application, a particular weapon to deployed or a travel direction in a game, and so forth.

[0057] Additionally, the images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118, may be used to conduct shared communication or networked interactivity in equipment operation, medical training, and/or remote/tele-operation guidance applications. Task specific gesture libraries or neural network machine learning could enable tool identification and feedback for a task. For example, a virtual tool that translates into remote, real actions may be enabled. In yet another example, the HMD system 1100 translates the manipulation of a virtual drill within a virtual scene to the remote operation of a drill on a robotic device deployed to search a collapsed building. Moreover, the HMD system 1100 may be programmable to the extent that it includes, for example, a protocol that enables the user to add a new gesture to a list of identifiable gestures associated with user actions.

[0058] In addition, the various cameras in the HMD 1100 may be configurable to detect spectrum frequencies in addition to the visible wavelengths of the spectrum. Multi-spectral imaging capabilities in the input cameras allows position tracking of the user and/or objects by eliminating nonessential image features (e.g., background noise). For example, in augmented reality (AR) applications such as surgery, instruments and equipment may be tracked by their infrared reflectivity without the need for additional tracking aids. Moreover, HMD 1100 could be employed in situations of low visibility where a “live feed” from the various cameras could be enhanced or augmented through computer analysis and displayed to the user as visual or audio cues.

[0059] The HMD system 1100 may also forego performing any type of data communication with a remote computing system or need power cables (e.g., independent mode of operation). In this regard, the HMD system 1100 may be a “cordless” device having a power unit that enables the HMD system 1100 to operate independently of external power systems. Accordingly, the user might play a full featured game without being tethered to another device (e.g., game console) or power supply. In a word processing example, the HMD system 1100 might present a virtual keyboard and/or virtual mouse on the displays 1104 and 1106 to provide a virtual desktop or word processing scene. Thus, gesture recognition data captured by one or more of the cameras may represent user typing activities on the virtual keyboard or movements of the virtual mouse. Advantages include, but are not limited to, ease of portability and privacy of the virtual desktop from nearby individuals. The underlying graphics processing architecture may support compression and/or decompression of video and audio signals. Moreover, providing separate images to the left eye and right eye of the user may facilitate the rendering, generation and/or perception of 3D scenes. The relative positions of the left-eye display 1104 and the right-eye display 1106 may also be adjustable to match variations in eye separation between different users.

[0060] The number of cameras illustrated in FIG. 8 is to facilitate discussion only. Indeed, the HMD system 1100 may include less than six or more than six cameras, depending on the circumstances.

[0061]* Functional Components of the HMD System *

[0062] FIG. 9 shows the HMD system in greater detail. In the illustrated example, the frame 1102 includes a power unit 1200 (e.g., battery power, adapter) to provide power to the HMD system. The illustrated frame 1102 also includes a motion tracking module 1220 (e.g., accelerometers, gyroscopes), wherein the motion tracking module 1220 provides motion tracking data, orientation data and/or position data to a processor system 1204. The processor system 1204 may include a network adapter 1224 that is coupled to an I/O bridge 1206. The I/O bridge 1206 may enable communications between the network adapter 1224 and various components such as, for example, audio input modules 1210, audio output modules 1208, a display device 1207, input cameras 1202, and so forth.

[0063] In the illustrated example, the audio input modules 1210 include a right-audio input 1218 and a left-audio input 1216, which detect sound that may be processed in order to recognize voice commands of the user as well as nearby individuals. The voice commands recognized in the captured audio signals may augment gesture recognition during modality switching and other applications. Moreover, the captured audio signals may provide 3D information that is used to enhance the immersive experience.

[0064] The audio output modules 1208 may include a right-audio output 1214 and a left-audio output 1212. The audio output modules 1208 may deliver sound to the ears of the user and/or other nearby individuals. The audio output modules 1208, which may be in the form of earbuds, on-ear speakers, over the ear speakers, loudspeakers, etc., or any combination thereof, may deliver stereo and/or 3D audio content to the user (e.g., spatial localization). The illustrated frame 1102 also includes a wireless module 1222, which may facilitate communications between the HMD system and various other systems (e.g., computers, wearable devices, game consoles). In one example, the wireless module 1222 communicates with the processor system 1204 via the network adapter 1224.

[0065] The illustrated display device 1207 includes the left-eye display 1104 and the right-eye display 1106, wherein the visual content presented on the displays 1104, 1106 may be obtained from the processor system 1204 via the I/O bridge 1206. The input cameras 1202 may include the left look-side camera 1116 the right look-side camera 1118, the left look-down camera 1108, the left look-front camera 1112, the right look-front camera 1114 and the right look-down camera 1110, already discussed.

[0066] Turning now FIG. 10, a general processing cluster (GPC) 1300 is shown. The illustrated GPC 1300 may be incorporated into a processing system such as, for example, the processor system 1204 (FIG. 9), already discussed. The GPC 1300 may include a pipeline manager 1302 that communicates with a scheduler. In one example, the pipeline manager 1302 receives tasks from the scheduler and distributes the tasks to one or more streaming multi-processors (SM’s) 1304. Each SM 1304 may be configured to process thread groups, wherein a thread group may be considered a plurality of related threads that execute the same or similar operations on different input data. Thus, each thread in the thread group may be assigned to a particular SM 1304. In another example, the number of threads may be greater than the number of execution units in the SM 1304. In this regard, the threads of a thread group may operate in parallel. The pipeline manager 1302 may also specify processed data destinations to a work distribution crossbar 1308, which communicates with a memory crossbar.

[0067] Thus, as each SM 1304 transmits a processed task to the work distribution crossbar 1308, the processed task may be provided to another GPC 1300 for further processing. The output of the SM 1304 may also be sent to a pre-raster operations (preROP) unit 1314, which in turn directs data to one or more raster operations units, or performs other operations (e.g., performing address translations, organizing picture color data, blending color, and so forth). The SM 1304 may include an internal level one (L1) cache (not shown) to which the SM 1304 may store data. The SM 1304 may also have access to a level two (L2) cache (not shown) via a memory management unit (MMU) 1310 and a level one point five (L1.5) cache 1306. The MMU 1310 may map virtual addresses to physical addresses. In this regard, the MMU 1310 may include page table entries (PTE’s) that are used to map virtual addresses to physical addresses of a tile, memory page and/or cache line index. The illustrated GPC 1300 also includes a texture unit 1312.

[0068] Graphics Pipeline Architecture

[0069] Turning now to FIG. 11, a graphics pipeline 1400 is shown. In the illustrated example, a world space pipeline 1420 includes a primitive distributor (PD) 1402. The PD 1402 may collect vertex data associated with high-order services, graphics primitives, triangles, etc., and transmit the vertex data to a vertex attribute fetch unit (VAF) 1404. The VAF 1404 may retrieve vertex attributes associated with each of the incoming vertices from shared memory and store the vertex data, along with the associated vertex attributes, into shared memory.

[0070] The illustrated world space pipeline 1420 also includes a vertex, tessellation, geometry processing unit (VTG) 1406. The VTG 1406 may include, for example, a vertex processing unit, a tessellation initialization processing unit, a task distributor, a task generation unit, a topology generation unit, a geometry processing unit, a tessellation processing unit, etc., or any combination thereof. In one example, the VTG 1406 is a programmable execution unit that is configured to execute geometry programs, tessellation programs, and vertex shader programs. The programs executed by the VTG 1406 may process the vertex data and vertex attributes received from the VAF 1404. Moreover, the programs executed by the VTG 1406 may produce graphics primitives, color values, surface normal factors and transparency values at each vertex for the graphics primitives for further processing within the graphics processing pipeline 1400.

[0071] The vertex processing unit of the VTG 1406 may be a programmable execution unit that executes vertex shader programs, lighting and transforming vertex data as specified by the vertex shader programs. For example, the vertex processing unit might be programmed to transform the vertex data from an object-based coordinate representation (e.g., object space) to an alternatively based coordinate system such as world space or normalize device coordinates (NDC) space. Additionally, the vertex processing unit may read vertex data and vertex attributes that are stored in shared memory by the VAF 1404 and process the vertex data and vertex attributes. In one example, the vertex processing unit stores processed vertices in shared memory.

[0072] The tessellation initialization processing unit (e.g., hull shader, tessellation control shader) may execute tessellation initialization shader programs. In one example, the tessellation initialization processing unit processes vertices produced by the vertex processing unit and generates graphics primitives sometimes referred to as “patches”. The tessellation initialization processing unit may also generate various patch attributes, wherein the patch data and the patch attributes are stored to shared memory. The task generation unit of the VTG 1406 may retrieve data and attributes for vertices and patches from shared memory. In one example, the task generation unit generates tasks for processing the vertices and patches for processing by the later stages in the graphics processing pipeline 1400.

[0073] The tasks produced by the task generation unit may be redistributed by the task distributor of the VTG 1406. For example, the tasks produced by the various instances of the vertex shader program and the tessellation initialization program may vary significantly between one graphics processing pipeline 1400 and another. Accordingly, the task distributor may redistribute these tasks such that each graphics processing pipeline 1400 has approximately the same workload during later pipeline stages.

[0074] As already noted, the VTG 1406 may also include a topology generation unit. In one example, the topology generation unit retrieves tasks distributed by the task distributor, indexes the vertices, including vertices associated with patches, and computes coordinates (UV) for tessellation vertices and the indices that connect the tessellation vertices to form graphics primitives. The indexed vertices may be stored by the topology generation unit in shared memory. The tessellation processing unit of the VTG 1406 may be configured to execute tessellation shader programs (e.g., domain shaders, tessellation evaluation shaders). The tessellation processing unit may read input data from shared memory and write output data to shared memory. The output data may be passed from the shared memory to the geometry processing unit (e.g., the next shader stage) as input data.

[0075] The geometry processing unit of the VTG 1406 may execute geometry shader programs to transform graphics primitives (e.g., triangles, line segments, points, etc.). In one example, vertices are grouped to construct graphics primitives, wherein the geometry processing unit subdivides the graphics primitives into one or more new graphics primitives. The geometry processing unit may also calculate parameters such as, for example, plain equation coefficients, that may be used to rasterize the new graphics primitives.

[0076] The illustrated world space pipeline 1420 also includes a viewport scale, cull, and clip unit (VPC) 1408 that receives the parameters and vertices specifying new graphics primitives from the VTG 1406. In one example, the VPC 1408 performs clipping, cuffing, perspective correction, and viewport transformation to identify the graphics primitives that are potentially viewable in the final rendered image. The VPC 1408 may also identify the graphics primitives that may not be viewable.

[0077] The graphics processing pipeline 1400 may also include a tiling unit 1410 coupled to the world space pipeline 1420. The tiling unit 1410 may be a graphics primitive sorting engine, wherein graphics primitives are processed in the world space pipeline 1420 and then transmitted to the tiling unit 1410. In this regard, the graphics processing pipeline 1400 may also include a screen space pipeline 1422, wherein the screen space may be divided into cache tiles. Each cache tile may therefore be associated with a portion of the screen space. For each graphics primitive, the tiling unit 1410 may identify the set of cache tiles that intersect with the graphics primitive (e.g., “tiling”). After tiling a number of graphics primitives, the tiling unit 1410 may process the graphics primitives on a cache tile basis. In one example, graphics primitives associated with a particular cache tile are transmitted to a setup unit 1412 in the screen space pipeline 1422 one tile at a time. Graphics primitives that intersect with multiple cache tiles may be processed once in the world space pipeline 1420, while being transmitted multiple times to the screen space pipeline 1422.

[0078] In one example, the setup unit 1412 receives vertex data from the VPC 1408 via the tiling unit 1410 and calculates parameters associated with the graphics primitives. The parameters may include, for example, edge equations, partial plane equations, and depth plain equations. The screen space pipeline 1422 may also include a rasterizer 1414 coupled to the setup unit 1412. The rasterizer may scan convert the new graphics primitives and transmit fragments and coverage data to a pixel shading unit (PS) 1416. The rasterizer 1414 may also perform Z culling and other Z-based optimizations.

[0079] The PS 1416, which may access shared memory, may execute fragment shader programs that transform fragments received from the rasterizer 1414. More particularly, the fragment shader programs may shade fragments at pixel-level granularity (e.g., functioning as pixel shader programs). In another example, the fragment shader programs shade fragments at sample-level granularity, where each pixel includes multiple samples, and each sample represents a portion of a pixel. Moreover, the fragment shader programs may shade fragments at any other granularity, depending on the circumstances (e.g., sampling rate). The PS 1416 may perform blending, shading, perspective correction, texture mapping, etc., to generate shaded fragments.

[0080] The illustrated screen space pipeline 1422 also includes a raster operations unit (ROP) 1418, which may perform raster operations such as, for example, stenciling, Z-testing, blending, and so forth. The ROP 1418 may then transmit pixel data as processed graphics data to one or more rendered targets (e.g., graphics memory). The ROP 1418 may be configured to compress Z or color data that is written to memory and decompress Z or color data that is read from memory. The location of the ROP 1418 may vary depending on the circumstances.

[0081] The graphics processing pipeline 1400 may be implemented by one or more processing elements. For example, the VTG 1406 and/or the PS 1416 may be implemented in one or more SM’s, the PD 1402, the VAF 1404, the VPC 1408, the tiling unit 1410, the setup unit 1412, the rasterizer 1414 and/or the ROP 1418 might be implemented in processing elements of a particular GPC in conjunction with a corresponding partition unit. The graphics processing pipeline 1400 may also be implemented in fixed-functionality hardware logic. Indeed, the graphics processing pipeline 1400 may be implemented in a PPU.

[0082] Thus, the illustrated world space pipeline 1420 processes graphics objects in 3D space, where the position of each graphics object is known relative to other graphics objects and relative to a 3D coordinate system. By contrast, the screen space pipeline 1422 may process graphics objects that have been projected from the 3D coordinate system onto a 2D planar surface that represents the surface of the display device. Additionally, the world space pipeline 1420 may be divided into an alpha phase pipeline and a beta phase pipeline, wherein the alpha phase pipeline includes pipeline stages from the PD 1402 through the task generation unit. The beta phase pipeline might include pipeline stages from the topology generation unit through the VPC 1408. In such a case, the graphics processing pipeline 1400 may perform a first set of operations (e.g., a single thread, a thread group, multiple thread groups acting in unison) in the alpha phase pipeline and a second set of operations (e.g., a single thread, a thread group, multiple thread groups acting in unison) in the beta phase pipeline.

[0083] If multiple graphics processing pipelines 1400 are in use, the vertex data and vertex attributes associated with a set of graphics objects may be divided so that each graphics processing pipeline 1400 has a similar workload through the alpha phase. Accordingly, alpha phase processing may substantially expand the amount of vertex data and vertex attributes, such that the amount of vertex data and vertex attributes produced by the task generation unit is significantly larger than the amount of vertex data and vertex attributes processed by the PD 1402 and the VAF 1404. Moreover, the task generation units associated with different graphics processing pipelines 1400 may produce vertex data and vertex attributes having different levels of quality, even when beginning the alpha phase with the same quantity of attributes. In such cases, the task distributor may redistribute the attributes produced by the alpha phase pipeline so that each graphics processing pipeline 1400 has approximately the same workload at the beginning of the beta phase pipeline.

[0084] Turning now to FIG. 12, a streaming multi-processor (SM) 1500 is shown. The illustrated SM 1500 includes K scheduler units 1504 coupled to an instruction cache 1502, wherein each scheduler unit 1504 receives a thread block array from a pipeline manager (not shown) and manages instruction scheduling for one or more thread blocks of each active thread block array. The scheduler unit 1504 may schedule threads for execution in groups of parallel threads, where each group may be referred to as a “warp”. Thus, each warp might include, for example, sixty-four threads. Additionally, the scheduler unit 1504 may manage a plurality of different thread blocks, allocating the thread blocks to warps for execution. The scheduler unit may then schedule instructions from the plurality of different warps on various functional units during each clock cycle. Each scheduler unit 1504 may include one or more instructions dispatch units 1522, wherein each dispatch unit 1522 transmits instructions to one or more of the functional units. The number of dispatch units 1522 may vary depending on the circumstances. In the illustrated example, the scheduler unit 1504 includes two dispatch units 1522 that enable two different instructions from the same warp to be dispatched during each clock cycle.

[0085] The SM 1500 may also include a register file 1506. The register file 1506 may include a set of registers that are divided between the functional units such that each functional unit is allocated a dedicated portion of the register file 1506. The register file 1506 may also be divided between different warps being executed by the SM 1500. In one example the register file 1506 provides temporary storage for operands connected to the data paths of the functional units. The illustrated SM 1500 also includes L processing cores 1508, wherein L may be a relatively large number (e.g., 192). Each core 1508 may be a pipelined, single-precision processing unit that includes a floating point arithmetic logic unit (e.g., IEEE 754-2008) as well as an integer arithmetic logic unit.

[0086] The illustrated SM 1500 also includes M double precision units (DPU’s) 1510, N special function units (SFU’s) 1512 and P load/store units (LSU’s) 1514. Each DPU 1510 may implement double-precision floating point arithmetic and each SFU 1512 may perform special functions such as, for example, rectangle copying pixel blending, etc. Additionally, each LSU 1514 may conduct load and store operations between a shared memory 1518 and the register file 1506. In one example, the load and store operations are conducted through J texture unit/L1 caches 1520 and an interconnected network 1516. In one example, the J texture unit/L1 caches 1520 are also coupled to a crossbar (not shown). Thus, the interconnect network 1516 may connect each of the functional units to the register file 1506 and to the shared memory 1518. In one example, the interconnect network 1516 functions as a crossbar that connects any of the functional units to any of the registers in the register file 1506.

[0087] The SM 1500 may be implemented within a graphics processor (e.g., graphics processing unit/GPU), wherein the texture unit/L1 caches 1520 may access texture maps from memory and sample the texture maps to produce sampled texture values for use in shader programs. Texture operations performed by the texture unit/L1 caches 1520 include, but are not limited to, antialiasing based on mipmaps.

[0088] System Overview Example

[0089] FIG. 13 is a block diagram of a processing system 1600, according to an embodiment. In various embodiments the system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 1602 or processor cores 1607. In on embodiment, the system 1600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0090] An embodiment of system 1600 can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments system 1600 is a mobile phone, smart phone, tablet computing device or mobile Internet device. Data processing system 1600 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, data processing system 1600 is a television or set top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0091] In some embodiments, the one or more processors 1602 each include one or more processor cores 1607 to process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, instruction set 1609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor cores 1607 may each process a different instruction set 1609, which may include instructions to facilitate the emulation of other instruction sets. Processor core 1607 may also include other processing devices, such a Digital Signal Processor (DSP).

[0092] In some embodiments, the processor 1602 includes cache memory 1604. Depending on the architecture, the processor 1602 can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 1607 using known cache coherency techniques. A register file 1606 is additionally included in processor 1602 which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 1602.

[0093] In some embodiments, processor 1602 is coupled to a processor bus 1610 to transmit communication signals such as address, data, or control signals between processor 1602 and other components in system 1600. In one embodiment the system 1600 uses an exemplary hub system architecture, including a memory controller hub 1616 and an Input Output (I/O) controller hub 1630. A memory controller hub 1616 facilitates communication between a memory device and other components of system 1600, while an I/O Controller Hub (ICH) 1630 provides connections to I/O devices via a local I/O bus. In one embodiment, the logic of the memory controller hub 1616 is integrated within the processor.

[0094] Memory device 1620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device 1620 can operate as system memory for the system 1600, to store data 1622 and instructions 1621 for use when the one or more processors 1602 executes an application or process. Memory controller hub 1616 also couples with an optional external graphics processor 1612, which may communicate with the one or more graphics processors 1608 in processors 1602 to perform graphics and media operations.

[0095] In some embodiments, ICH 1630 enables peripherals to connect to memory device 1620 and processor 1602 via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., hard disk drive, flash memory, etc.), and a legacy I/O controller 1640 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices, such as keyboard and mouse 1644 combinations. A network controller 1634 may also couple to ICH 1630. In some embodiments, a high-performance network controller (not shown) couples to processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, the I/O controller hub 1630 may be integrated within the one or more processor 1602, or the memory controller hub 1616 and I/O controller hub 1630 may be integrated into a discreet external graphics processor, such as the external graphics processor 1612.

[0096] FIG. 14 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A-1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Those elements of FIG. 14 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor 1700 can include additional cores up to and including additional core 1702N represented by the dashed lined boxes. Each of processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments each processor core also has access to one or more shared cached units 1706.

[0097] The internal cache units 1704A-1704N and shared cache units 1706 represent a cache memory hierarchy within the processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 1706 and 1704A-1704N.

[0098] In some embodiments, processor 1700 may also include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). System agent core 1710 provides management functionality for the various processor components. In some embodiments, system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0099] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multi-threading. In such embodiment, the system agent core 1710 includes components for coordinating and operating cores 1702A-1702N during multi-threaded processing. System agent core 1710 may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 1702A-1702N and graphics processor 1708.

[0100] In some embodiments, processor 1700 additionally includes graphics processor 1708 to execute graphics processing operations. In some embodiments, the graphics processor 1708 couples with the set of shared cache units 1706, and the system agent core 1710, including the one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 is coupled with the graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 1711 may be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 1708 or system agent core 1710.

[0101] In some embodiments, a ring based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor 1708 couples with the ring interconnect 1712 via an I/O link 1713.

[0102] The exemplary I/O link 1713 represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702-1702N and graphics processor 1708 use embedded memory modules 1718 as a shared Last Level Cache.

[0103] In some embodiments, processor cores 1702A-1702N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores 1702A-1702N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 1702A-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor cores 1702A-1702N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor 1700 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

[0104] FIG. 15 is a block diagram of a graphics processor 1800, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor 1800 includes a memory interface 1814 to access memory. Memory interface 1814 can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

[0105] In some embodiments, graphics processor 1800 also includes a display controller 1802 to drive display output data to a display device 1820. Display controller 1802 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. In some embodiments, graphics processor 1800 includes a video codec engine 1806 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[0106] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 1810. In some embodiments, graphics processing engine 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0107] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline 1812 includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system 1815. While 3D pipeline 1812 can be used to perform media operations, an embodiment of GPE 1810 also includes a media pipeline 1816 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0108] In some embodiments, media pipeline 1816 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 1806. In some embodiments, media pipeline 1816 additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system 1815. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system 1815.

[0109] In some embodiments, 3D/Media subsystem 1815 includes logic for executing threads spawned by 3D pipeline 1812 and media pipeline 1816. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

[0110] 3D/Media Processing

[0111] FIG. 16 is a block diagram of a graphics processing engine 1910 of a graphics processor in accordance with some embodiments. In one embodiment, the GPE 1910 is a version of the GPE 1810 shown in FIG. 15. Elements of FIG. 16 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0112] In some embodiments, GPE 1910 couples with a command streamer 1903, which provides a command stream to the GPE 3D and media pipelines 1912, 1916. In some embodiments, command streamer 1903 is coupled to memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 1903 receives commands from the memory and sends the commands to 3D pipeline 1912 and/or media pipeline 1916. The commands are directives fetched from a ring buffer, which stores commands for the 3D and media pipelines 1912, 1916. In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The 3D and media pipelines 1912, 1916 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to an execution unit array 1914. In some embodiments, execution unit array 1914 is scalable, such that the array includes a variable number of execution units based on the target power and performance level of GPE 1910.

[0113] In some embodiments, a sampling engine 1930 couples with memory (e.g., cache memory or system memory) and execution unit array 1914. In some embodiments, sampling engine 1930 provides a memory access mechanism for execution unit array 1914 that allows execution array 1914 to read graphics and media data from memory. In some embodiments, sampling engine 1930 includes logic to perform specialized image sampling operations for media.

[0114] In some embodiments, the specialized media sampling logic in sampling engine 1930 includes a de-noise/de-interlace module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, de-noise/de-interlace module 1932 includes logic to perform one or more of a de-noise or a de-interlace algorithm on decoded video data. The de-interlace logic combines alternating fields of interlaced video content into a single fame of video. The de-noise logic reduces or removes data noise from video and image data. In some embodiments, the de-noise logic and de-interlace logic are motion adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the de-noise/de-interlace module 1932 includes dedicated motion detection logic (e.g., within the motion estimation engine 1934).

[0115] In some embodiments, motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions such as motion vector estimation and prediction on video data. The motion estimation engine determines motion vectors that describe the transformation of image data between successive video frames. In some embodiments, a graphics processor media codec uses video motion estimation engine 1934 to perform operations on video at the macro-block level that may otherwise be too computationally intensive to perform with a general-purpose processor. In some embodiments, motion estimation engine 1934 is generally available to graphics processor components to assist with video decode and processing functions that are sensitive or adaptive to the direction or magnitude of the motion within video data.

[0116] In some embodiments, image scaling and filtering module 1936 performs image-processing operations to enhance the visual quality of generated images and video. In some embodiments, scaling and filtering module 1936 processes image and video data during the sampling operation before providing the data to execution unit array 1914.

[0117] In some embodiments, the GPE 1910 includes a data port 1944, which provides an additional mechanism for graphics subsystems to access memory. In some embodiments, data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, scratch memory space reads/writes, and media surface accesses. In some embodiments, data port 1944 includes cache memory space to cache accesses to memory. The cache memory can be a single data cache or separated into multiple caches for the multiple subsystems that access memory via the data port (e.g., a render buffer cache, a constant buffer cache, etc.). In some embodiments, threads executing on an execution unit in execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect that couples each of the sub-systems of GPE 1910.

[0118] Execution Units

[0119] FIG. 17 is a block diagram of another embodiment of a graphics processor 2000. Elements of FIG. 17 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0120] In some embodiments, graphics processor 2000 includes a ring interconnect 2002, a pipeline front-end 2004, a media engine 2037, and graphics cores 2080A-2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0121] In some embodiments, graphics processor 2000 receives batches of commands via ring interconnect 2002. The incoming commands are interpreted by a command streamer 2003 in the pipeline front-end 2004. In some embodiments, graphics processor 2000 includes scalable execution logic to perform 3D geometry processing and media processing via the graphics core(s) 2080A-2080N. For 3D geometry processing commands, command streamer 2003 supplies commands to geometry pipeline 2036. For at least some media processing commands, command streamer 2003 supplies the commands to a video front end 2034, which couples with a media engine 2037. In some embodiments, media engine 2037 includes a Video Quality Engine (VQE) 2030 for video and image post-processing and a multi-format encode/decode (MFX) 2033 engine to provide hardware-accelerated media data encode and decode. In some embodiments, geometry pipeline 2036 and media engine 2037 each generate execution threads for the thread execution resources provided by at least one graphics core 2080A.

[0122] In some embodiments, graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A-2080N (sometimes referred to as core slices), each having multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In some embodiments, graphics processor 2000 can have any number of graphics cores 2080A through 2080N. In some embodiments, graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second core sub-core 2060A. In other embodiments, the graphics processor is a low power processor with a single sub-core (e.g., 2050A). In some embodiments, graphics processor 2000 includes multiple graphics cores 2080A-2080N, each including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. Each sub-core in the set of first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media/texture samplers 2054A-2054N. Each sub-core in the set of second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In some embodiments, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in the various embodiments of the graphics processor.

[0123] FIG. 18 illustrates thread execution logic 2100 including an array of processing elements employed in some embodiments of a GPE. Elements of FIG. 18 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0124] In some embodiments, thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, instruction cache 2106, a scalable execution unit array including a plurality of execution units 2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, thread execution logic 2100 includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache 2106, data port 2114, sampler 2110, and execution unit array 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit array 2108A-2108N includes any number individual execution units.

[0125] In some embodiments, execution unit array 2108A-2108N is primarily used to execute “shader” programs. In some embodiments, the execution units in array 2108A-2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders).

[0126] Each execution unit in execution unit array 2108A-2108N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A-2108N support integer and floating-point data types.

[0127] The execution unit instruction set includes single instruction multiple data (SIMD) instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0128] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.

[0129] During execution, the graphics and media pipelines send thread initiation requests to thread execution logic 2100 via thread spawning and dispatch logic. In some embodiments, thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics and media pipelines and instantiates the requested threads on one or more execution units 2108A-2108N. For example, the geometry pipeline (e.g., 2036 of FIG. 17) dispatches vertex processing, tessellation, or geometry processing threads to thread execution logic 2100 (FIG. 18). In some embodiments, thread dispatcher 2104 can also process runtime thread spawning requests from the executing shader programs.

[0130] Once a group of geometric objects has been processed and rasterized into pixel data, pixel shader 2102 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, pixel shader 2102 calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some embodiments, pixel shader 2102 then executes an application programming interface (API)-supplied pixel shader program. To execute the pixel shader program, pixel shader 2102 dispatches threads to an execution unit (e.g., 2108A) via thread dispatcher 2104. In some embodiments, pixel shader 2102 uses texture sampling logic in sampler 2110 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

[0131] In some embodiments, the data port 2114 provides a memory access mechanism for the thread execution logic 2100 output processed data to memory for processing on a graphics processor output pipeline. In some embodiments, the data port 2114 includes or couples to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0132] FIG. 19 is a block diagram illustrating a graphics processor instruction formats 2200 according to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, instruction format 2200 described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.

[0133] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit format 2210. A 64-bit compacted instruction format 2230 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field 2213. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit format 2210.

[0134] For each format, instruction opcode 2212 defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, instruction control field 2214 enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For 128-bit instructions 2210 an exec-size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field 2216 is not available for use in the 64-bit compact instruction format 2230.

[0135] Some execution unit instructions have up to three operands including two source operands, src0 2220, src1 2222, and one destination 2218. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. An instruction’s last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

[0136] In some embodiments, the 128-bit instruction format 2210 includes an access/address mode information 2226 specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction 2210.

[0137] In some embodiments, the 128-bit instruction format 2210 includes an access/address mode field 2226, which specifies an address mode and/or an access mode for the instruction. In one embodiment the access mode to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction 2210 may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction 2210 may use 16-byte-aligned addressing for all source and destination operands.

[0138] In one embodiment, the address mode portion of the access/address mode field 2226 determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction 2210 directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.

[0139] In some embodiments instructions are grouped based on opcode 2212 bit-fields to simplify Opcode decode 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode group 2242 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 2242 shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group 2246 includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs the arithmetic operations in parallel across data channels. The vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

[0140]* Graphics Pipeline *

[0141] FIG. 20 is a block diagram of another embodiment of a graphics processor 2300. Elements of FIG. 20 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0142] In some embodiments, graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 2300 via a ring interconnect 2302. In some embodiments, ring interconnect 2302 couples graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 2302 are interpreted by a command streamer 2303, which supplies instructions to individual components of graphics pipeline 2320 or media pipeline 2330.

[0143] In some embodiments, command streamer 2303 directs the operation of a vertex fetcher 2305 that reads vertex data from memory and executes vertex-processing commands provided by command streamer 2303. In some embodiments, vertex fetcher 2305 provides vertex data to a vertex shader 2307, which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcher 2305 and vertex shader 2307 execute vertex-processing instructions by dispatching execution threads to execution units 2352A, 2352B via a thread dispatcher 2331.

[0144] In some embodiments, execution units 2352A, 2352B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 2352A, 2352B have an attached L1 cache 2351 that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0145] In some embodiments, graphics pipeline 2320 includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operations. A programmable domain shader 2317 provides back-end evaluation of tessellation output. A tessellator 2313 operates at the direction of hull shader 2311 and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to graphics pipeline 2320. In some embodiments, if tessellation is not used, tessellation components 2311, 2313, 2317 can be bypassed.

[0146] In some embodiments, complete geometric objects can be processed by a geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, geometry shader 2319 is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

[0147] Before rasterization, a clipper 2329 processes vertex data. The clipper 2329 may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer 2373 (e.g., depth test component) in the render output pipeline 2370 dispatches pixel shaders to convert the geometric objects into their per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 2350. In some embodiments, an application can bypass the rasterizer 2373 and access un-rasterized vertex data via a stream out unit 2323.

[0148] The graphics processor 2300 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution units 2352A, 2352B and associated cache(s) 2351, texture and media sampler 2354, and texture/sampler cache 2358 interconnect via a data port 2356 to perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler 2354, caches 2351, 2358 and execution units 2352A, 2352B each have separate memory access paths.

[0149] In some embodiments, render output pipeline 2370 contains a rasterizer 2373 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache 2378 and depth cache 2379 are also available in some embodiments. A pixel operations component 2377 performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g., bit block image transfers with blending) are performed by the 2D engine 2341, or substituted at display time by the display controller 2343 using overlay display planes. In some embodiments, a shared L3 cache 2375 is available to all graphics components, allowing the sharing of data without the use of main system memory.

[0150] In some embodiments, graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, video front end 2334 receives pipeline commands from the command streamer 2303. In some embodiments, media pipeline 2330 includes a separate command streamer. In some embodiments, video front-end 2334 processes media commands before sending the command to the media engine 2337. In some embodiments, media engine 2337 includes thread spawning functionality to spawn threads for dispatch to thread execution logic 2350 via thread dispatcher 2331.

[0151] In some embodiments, graphics processor 2300 includes a display engine 2340. In some embodiments, display engine 2340 is external to processor 2300 and couples with the graphics processor via the ring interconnect 2302, or some other interconnect bus or fabric. In some embodiments, display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, display engine 2340 contains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller 2343 couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

[0152] In some embodiments, graphics pipeline 2320 and media pipeline 2330 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct3D library from the Microsoft Corporation, or support may be provided to both OpenGL and D3D. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

[0153] Graphics Pipeline Programming

[0154] FIG. 21A is a block diagram illustrating a graphics processor command format 2400 according to some embodiments. FIG. 21B is a block diagram illustrating a graphics processor command sequence 2410 according to an embodiment. The solid lined boxes in FIG. 21A illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format 2400 of FIG. 21A includes data fields to identify a target client 2402 of the command, a command operation code (opcode) 2404, and the relevant data 2406 for the command. A sub-opcode 2405 and a command size 2408 are also included in some commands.

[0155] In some embodiments, client 2402 specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode 2404 and, if present, sub-opcode 2405 to determine the operation to perform. The client unit performs the command using information in data field 2406. For some commands an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word.

[0156] The flow diagram in FIG. 21B shows an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

[0157] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline flush command 2412 to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked dirty can be flushed to memory. In some embodiments, pipeline flush command 2412 can be used for pipeline synchronization or before placing the graphics processor into a low power state.

[0158] In some embodiments, a pipeline select command 2413 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command 2413 is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command is 2412 is required immediately before a pipeline switch via the pipeline select command 2413.

[0159] In some embodiments, a pipeline control command 2414 configures a graphics pipeline for operation and is used to program the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, pipeline control command 2414 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 2414 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

[0160] In some embodiments, return buffer state commands 2416 are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state 2416 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0161] The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination 2420, the command sequence is tailored to the 3D pipeline 2422 beginning with the 3D pipeline state 2430, or the media pipeline 2424 beginning at the media pipeline state 2440.

[0162] The commands for the 3D pipeline state 2430 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based the particular 3D API in use. In some embodiments, 3D pipeline state 2430 commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

[0163] In some embodiments, 3D primitive 2432 command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive 2432 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2432 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 2432 command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline 2422 dispatches shader execution threads to graphics processor execution units.

[0164] In some embodiments, 3D pipeline 2422 is triggered via an execute 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a go or kick command in the command sequence. In one embodiment command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.

[0165] In some embodiments, the graphics processor command sequence 2410 follows the media pipeline 2424 path when performing media operations. In general, the specific use and manner of programming for the media pipeline 2424 depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

[0166] In some embodiments, media pipeline 2424 is configured in a similar manner as the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into in a command queue before the media object commands 2442. In some embodiments, media pipeline state commands 2440 include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, media pipeline state commands 2440 also support the use one or more pointers to “indirect” state elements that contain a batch of state settings.

[0167] In some embodiments, media object commands 2442 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing a media object command 2442. Once the pipeline state is configured and media object commands 2442 are queued, the media pipeline 2424 is triggered via an execute command 2444 or an equivalent execute event (e.g., register write). Output from media pipeline 2424 may then be post processed by operations provided by the 3D pipeline 2422 or the media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

[0168] Graphics Software Architecture

[0169] FIG. 22 illustrates exemplary graphics software architecture for a data processing system 2500 according to some embodiments. In some embodiments, software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes a graphics processor 2532 and one or more general-purpose processor core(s) 2534. The graphics application 2510 and operating system 2520 each execute in the system memory 2550 of the data processing system.

[0170] In some embodiments, 3D graphics application 2510 contains one or more shader programs including shader instructions 2512. The shader language instructions may be in a high-level shader language, such as the High Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in a machine language suitable for execution by the general-purpose processor core 2534. The application also includes graphics objects 2516 defined by vertex data.

[0171] In some embodiments, operating system 2520 is a Microsoft.RTM. Windows.RTM. operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 2510.

[0172] In some embodiments, user mode graphics driver 2526 contains a back-end shader compiler 2527 to convert the shader instructions 2512 into a hardware specific representation. When the OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to a user mode graphics driver 2526 for compilation. In some embodiments, user mode graphics driver 2526 uses operating system kernel mode functions 2528 to communicate with a kernel mode graphics driver 2529. In some embodiments, kernel mode graphics driver 2529 communicates with graphics processor 2532 to dispatch commands and instructions.

[0173]* IP Core Implementations *

[0174] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0175] FIG. 23 is a block diagram illustrating an IP core development system 2600 that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2600 may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility 2630 can generate a software simulation 2610 of an IP core design in a high level programming language (e.g., C/C++). The software simulation 2610 can be used to design, test, and verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized from the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design 2615, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

[0176] The RTL design 2615 or equivalent may be further synthesized by the design facility into a hardware model 2620, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3.sup.rd party fabrication facility 2665 using non-volatile memory 2640 (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 2650 or wireless connection 2660. The fabrication facility 2665 may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0177] FIG. 24 is a block diagram illustrating an exemplary system on a chip integrated circuit 2700 that may be fabricated using one or more IP cores, according to an embodiment. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may additionally include an image processor 2715 and/or a video processor 2720, any of which may be a modular IP core from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic including a USB controller 2725, UART controller 2730, an SPI/SDIO controller 2735, and an I.sup.2S/I.sup.2C controller 2740. Additionally, the integrated circuit can include a display device 2745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760 including flash memory and a flash memory controller. Memory interface may be provided via a memory controller 2765 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0178] Additionally, other logic and circuits may be included in the processor of integrated circuit 2700, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

[0179] Advantageously, any of the above systems, processors, graphics processors, apparatuses, and/or methods may be integrated or configured with any of the various embodiments described herein (e.g., or portions thereof), including, for example, those described in the following Additional Notes and Examples.

Additional Notes and Examples

[0180] Example 1 may include an electronic processing system, comprising a graphics processor, memory communicatively coupled to the graphics processor, a render subsystem communicatively coupled to the graphics processor, and a parameter adjuster communicatively coupled to the render subsystem to adjust a render parameter of the render subsystem based on a vision profile associated with a user.

[0181] Example 2 may include the system of Example 1, further comprising a vision profile developer communicatively coupled to the parameter adjuster to develop the vision profile associated with the user.

[0182] Example 3 may include the system of Example 2, wherein the vision profile developer is further to test a vision of the user to develop the vision profile.

[0183] Example 4 may include the system of Example 2, wherein the vision profile developer is further to identify the user, and load a vision profile associated with the identified user.

[0184] Example 5 may include the system of any of Examples 1 to 4, wherein the vision profile includes information related to one or more of visual acuity, color perception, and depth perception.

[0185] Example 6 may include the system of any of Examples 1 to 4, wherein the render parameter includes one or more of a level of detail parameter, a resolution parameter, a color precision parameter, and a stereo render parameter.

[0186] Example 7 may include a graphics apparatus, comprising a vision characterizer to determine a vision characteristic associated with a user, and a parameter adjuster communicatively coupled to the vision characterizer to adjust a render parameter of a graphics system based on the determined vision characteristic.

[0187] Example 8 may include the apparatus of Example 7, further comprising a vision profile developer communicatively coupled to the vision characterizer to develop a vision profile associated with the user.

[0188] Example 9 may include the apparatus of Example 8, wherein the vision profile developer is further to test a vision of the user to develop the vision profile.

[0189] Example 10 may include the apparatus of Example 8, wherein the vision profile developer is further to identify the user, and load a vision profile associated with the identified user.

[0190] Example 11 may include the apparatus of any of Examples 8 to 10, wherein the vision profile includes information related to one or more of visual acuity, color perception, and depth perception.

[0191] Example 12 may include the apparatus of any of Examples 7 to 10, wherein the render parameter includes one or more of a level of detail parameter, a resolution parameter, a color precision parameter, and a stereo render parameter.

[0192] Example 13 may include a method of adjusting a graphics parameter, comprising determining a vision characteristic associated with a user, and adjusting a render parameter of a graphics system based on the determined vision characteristic.

[0193] Example 14 may include the method of Example 13, further comprising developing a vision profile associated with the user.

[0194] Example 15 may include the method of Example 14, further comprising testing a vision of the user to develop the vision profile.

[0195] Example 16 may include the method of Example 14, further comprising identifying the user, and loading a vision profile associated with the identified user.

[0196] Example 17 may include the method of any of Examples 14 to 16, wherein the vision profile includes information related to one or more of visual acuity, color perception, and depth perception.

[0197] Example 18 may include the method of any of Examples 13 to 16, wherein the render parameter includes one or more of a level of detail parameter, a resolution parameter, a color precision parameter, and a stereo render parameter.

[0198] Example 19 may include at least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to determine a vision characteristic associated with a user, and adjust a render parameter of a graphics system based on the determined vision characteristic.

[0199] Example 20 may include the at least one computer readable medium of Example 19, comprising a further set of instructions, which when executed by the computing device, cause the computing device to develop a vision profile associated with the user.

[0200] Example 21 may include the at least one computer readable medium of Example 20, comprising a further set of instructions, which when executed by the computing device, cause the computing device to test a vision of the user to develop the vision profile.

[0201] Example 22 may include the at least one computer readable medium of Example 20, comprising a further set of instructions, which when executed by the computing device, cause the computing device to identify the user, and load a vision profile associated with the identified user.

[0202] Example 23 may include the at least one computer readable medium of any of Example 20 to 22, wherein the vision profile includes information related to one or more of visual acuity, color perception, and depth perception.

[0203] Example 24 may include the at least one computer readable medium of any of Example 19 to 22, wherein the render parameter includes one or more of a level of detail parameter, a resolution parameter, a color precision parameter, and a stereo render parameter.

[0204] Example 25 may include a graphics apparatus, comprising means for determining a vision characteristic associated with a user, and means for adjusting a render parameter of a graphics system based on the determined vision characteristic.

[0205] Example 26 may include the apparatus of Example 25, further comprising means for developing a vision profile associated with the user.

[0206] Example 27 may include the apparatus of Example 26, further comprising means for testing a vision of the user to develop the vision profile.

[0207] Example 28 may include the apparatus of Example 26, further comprising means for identifying the user, and means for loading a vision profile associated with the identified user.

[0208] Example 29 may include the apparatus of any of Examples 26 to 28, wherein the vision profile includes information related to one or more of visual acuity, color perception, and depth perception.

[0209] Example 30 may include the apparatus of any of Examples 25 to 28, wherein the render parameter includes one or more of a level of detail parameter, a resolution parameter, a color precision parameter, and a stereo render parameter.

[0210] Embodiments are applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

[0211] Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0212] The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first”, “second”, etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

[0213] As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrase “one or more of A, B, and C” and the phrase “one or more of A, B, or C” both may mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0214] Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.