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Facebook Patent | Reducing the planarity variation in a display device

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Patent: Reducing the planarity variation in a display device

Drawings: Click to check drawins

Publication Number: 20210013099

Publication Date: 20210114

Applicant: Facebook

Abstract

Disclosed herein are techniques for reducing a variation in the planarity of a display device. In some embodiments, a method includes applying a first pressure to a top surface of a display device at a first temperature. The display device includes a backplane, a plurality of dies, and a plurality of fusible interconnections between the backplane and the plurality of dies. The first pressure is applied in a direction that is perpendicular to a plane of the backplane on which the plurality of dies are arranged. The first pressure and the first temperature are selected to cause the plurality of fusible interconnections to absorb variations in a planarity of the top surface of the display device.

Claims

  1. A method comprising: applying a first pressure to a top surface of a display device at a first temperature, wherein: the display device includes a backplane, a plurality of dies, and a plurality of fusible interconnections between the backplane and the plurality of dies, the first pressure is applied in a direction that is perpendicular to a plane of the backplane on which the plurality of dies are arranged, and the first pressure and the first temperature are selected to cause the plurality of fusible interconnections to absorb variations in a planarity of the top surface of the display device.

  2. The method of claim 1, wherein the first pressure is provided solely by a weight of a material that is placed on the top surface of the display device.

  3. The method of claim 2, wherein the first temperature corresponds to a melting point of the plurality of fusible interconnections.

  4. The method of claim 2, wherein a bottom surface of the material that contacts the top surface of the display device is flat.

  5. The method of claim 2, wherein a bottom surface of the material that contacts the top surface of the display device is curved.

  6. The method of claim 5, wherein a curvature of the bottom surface of the material is determined based on a warpage of the top surface of the display device that is predicted to occur after a reflow of a fusible material that forms the plurality of fusible interconnections.

  7. The method of claim 1, wherein: the first pressure corresponds to a yield strength of a fusible material of the plurality of fusible interconnections at room temperature, and the first pressure is provided by a weight of a material that is placed on the top surface of the display device and an external force that is applied to the material.

  8. The method of claim 7, wherein the first temperature corresponds to the room temperature.

  9. The method of claim 7, wherein a bottom surface of the material that contacts the top surface of the display device is flat.

  10. The method of claim 7, wherein a bottom surface of the material that contacts the top surface of the display device is curved.

  11. The method of claim 7, wherein the fusible material comprises solder.

  12. The method of claim 1, further comprising: applying a second pressure to the top surface of the display device at a second temperature, wherein: the second pressure is applied after the first pressure is applied, the second pressure is applied in the direction that is perpendicular to the plane of the backplane on which the plurality of dies are arranged, and the second pressure and the second temperature are selected to cause the plurality of fusible interconnections to absorb further variations in the planarity of the top surface of the display device.

  13. The method of claim 12, wherein: the first pressure is provided solely by a weight of a material that is placed on the top surface of the display device, and the second pressure is provided by the weight of the material that is placed on the top surface of the display device and an external force that is applied to the material.

  14. The method of claim 1, further comprising applying a protective film to the top surface of the display device before applying the first pressure to the top surface of the display device.

  15. The method of claim 14, wherein the protective film comprises an electronic grade Si film adhesive or a thermoplastic material.

  16. The method of claim 1, wherein the display device further includes at least one spacer that is arranged adjacent to the plurality of dies.

  17. The method of claim 1, wherein a fusible material of the plurality of the fusible interconnections comprises solder.

  18. A display device comprising: a backplane; a plurality of dies, wherein each die of the plurality of dies comprises a plurality of light emitting diodes; and a plurality of fusible interconnections between the backplane and the plurality of dies, wherein a planarity variation of a top surface of the display device is less than 10 .mu.m.

  19. The display device of claim 18, further comprising at least one spacer that is arranged adjacent to the plurality of dies.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority under 35 U.S.C. .sctn. 119 to U.S. Provisional Patent Application No. 62/872,573, filed on Jul. 10, 2019, and U.S. Provisional Patent Application No. 62/877,119, filed on Jul. 22, 2019, the contents of which are hereby incorporated by reference in their entireties for all purposes.

BACKGROUND

[0002] The disclosure relates generally to display, and more specifically, to integration of display devices with control circuits.

[0003] Displays are ubiquitous and are a core component of wearable devices, smart phones, tablets, laptops, desktops, TVs and display systems. Common display technologies today include Light Emitting Diode (LED) displays. A display device can include a plurality of LED dies that are mounted on a backplane.

SUMMARY

[0004] The present disclosure generally relates to reducing a variation in the planarity of a display device. In some embodiments, a method includes applying a first pressure to a top surface of a display device at a first temperature. The display device includes a backplane, a plurality of dies, and a plurality of fusible interconnections between the backplane and the plurality of dies. The first pressure is applied in a direction that is perpendicular to a plane of the backplane on which the plurality of dies are arranged. The first pressure and the first temperature are selected to cause the plurality of fusible interconnections to absorb variations in a planarity of the top surface of the display device.

[0005] The first pressure may be provided solely by a weight of a material that is placed on the top surface of the display device. The first temperature may correspond to a melting point of the plurality of fusible interconnections. A bottom surface of the material that contacts the top surface of the display device may be flat. Alternatively, a bottom surface of the material that contacts the top surface of the display device may be curved. A curvature of the bottom surface of the material may be determined based on a warpage of the top surface of the display device that is predicted to occur after a reflow of a fusible material that forms the plurality of fusible interconnections.

[0006] Alternatively, the first pressure may correspond to a yield strength of a fusible material of the plurality of fusible interconnections at room temperature, and the first pressure may be provided by a weight of a material that is placed on the top surface of the display device and an external force that is applied to the material. The first temperature may correspond to the room temperature. A bottom surface of the material that contacts the top surface of the display device may be flat. Alternatively, a bottom surface of the material that contacts the top surface of the display device may be curved. The fusible material may include solder.

[0007] The method may also include applying a second pressure to the top surface of the display device at a second temperature. The second pressure may be applied after the first pressure is applied. The second pressure may be applied in the direction that is perpendicular to the plane of the backplane on which the plurality of dies are arranged. The second pressure and the second temperature are selected to cause the plurality of fusible interconnections to absorb further variations in the planarity of the top surface of the display device. The first pressure may be provided solely by a weight of a material that is placed on the top surface of the display device, and the second pressure may be provided by the weight of the material that is placed on the top surface of the display device and an external force that is applied to the material.

[0008] The method may also include applying a protective film to the top surface of the display device before applying the first pressure to the top surface of the display device. The protective film may include an electronic grade Si film adhesive or a thermoplastic material. The display device may also include at least one spacer that is arranged adjacent to the plurality of dies.

[0009] In some embodiments, a display device includes a backplane, a plurality of dies, and a plurality of fusible interconnections between the backplane and the plurality of dies. Each die of the plurality of dies includes a plurality of light emitting diodes. A planarity variation of a top surface of the display device is less than 10 .mu.m. The display device may also include at least one spacer that is arranged adjacent to the plurality of dies.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Illustrative embodiments are described with reference to the following figures:

[0011] FIG. 1 shows a cross-sectional view of an example LED device that can be manufactured using examples of the disclosed techniques.

[0012] FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F are schematic views of an example display that can be manufactured using examples of the disclosed techniques.

[0013] FIG. 3 illustrates an example of a display device, according to examples of the disclosed techniques.

[0014] FIG. 4A and FIG. 4B illustrate examples of the display device of FIG. 3, according to examples of the disclosed techniques.

[0015] FIG. 5A and FIG. 5B illustrate examples of the display device of FIG. 3, according to examples of the disclosed techniques.

[0016] FIG. 6 illustrates examples of the display device of FIG. 3, according to examples of the disclosed techniques.

[0017] FIG. 7A, FIG. 7B, FIG. 7C, and FIG. 7D illustrate examples of the display device of FIG. 3, according to examples of the disclosed techniques.

[0018] FIG. 8 illustrates an example of a method for manufacturing a display device, according to examples of the disclosed techniques.

[0019] FIG. 9A, FIG. 9B, and FIG. 9C illustrate an example of a method for reducing the planarity variation in a display device.

[0020] The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated may be employed without departing from the principles, or benefits touted, of this disclosure.

[0021] In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

DETAILED DESCRIPTION

[0022] In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive.

[0023] Common display technologies today range from Liquid Crystal Displays (LCDs) to more recent Organic Light Emitting Diode (OLED) displays and Active Matrix Organic Light Emitting Diode (AMOLED) displays. Inorganic Light Emitting Diodes (ILEDs) are emerging as the third generation of flat display image generators based on superior battery performance and enhanced brightness. A “.mu.LED,” “uLED,” or “MicroLED,” described herein refers to a particular type of ILED having a small active light emitting area (e.g., less than 2,000 .mu.m.sup.2) and, in some examples, being capable of generating directional light to increase the brightness level of light emitted from the small active light emitting area. In some examples, a micro-LED may refer to an LED that has an active light emitting area that is less than 50 .mu.m, less than 20 .mu.m, or less than 10 .mu.m. In some examples, the linear dimension may be as small as 2 .mu.m or 4 .mu.m. For the rest of the disclosure, “LED” may refer .mu.LED, ILED, OLED, or any type of LED devices.

[0024] ILED displays can be manufactured using different processes from OLED displays. For example, OLED devices are fabricated directly onto a display substrate. In contrast, ILED devices are fabricated separately from the display substrate. The base material of ILED devices base material is grown on a crystalline substrate to form an LED starter wafer. The LED starter wafer can be processed through various steps to produce individual LED dies, with each LED die including an LED device. Once fabricated, the LED dies can be transferred from the carrier substrate to a backplane. The backplane can be a display backplane of a display device. The LED devices of the display device can be divided to form pixels.

[0025] The backplane, as well as other components such as control circuits and power system can be individually attached to a circuit board (e.g., a printed circuit board (PCB)) to form a display system. The circuit board can provide electrical connections among the different components of the display system. Such arrangements can be undesirable. First, as the components are spaced apart by relatively long distances, the form factor of the display system increases, which makes it difficult to deploy the display system in devices with very limited spaces, such as a wearable device. Second, long signal traces are needed to provide the electrical connections among the components. The long signal traces can add substantial delay to the transmission of high speed signals, such as high resolution image data, which can significantly degrade the performance of the display system. All these can limit the applications of the display system.

[0026] Examples of the present disclosure provide a display apparatus. The display apparatus comprises an integrated circuit (IC) chip. The IC chip comprises light emitting diode (LED) devices, a first die, and a second die integrated within the IC chip. The LED devices are exposed on a front side of the IC chip. The IC chip further includes input/output (I/O) bumps on a back side of the IC chip. The LED devices can form a stack with the first die along a vertical direction. The first die includes driver circuits electrically connected to the LED devices and is electrically connected to at least some of the I/O bumps. The IC chip further includes a first circuit that extends along the vertical direction from the front side of the IC chip towards a back side of the IC chip and across at least a thickness of the first die to provide electrical connections between the LED devices and at least some of the I/O bumps. The second die, which comprises a display engine and control circuits for the driver circuits of the first die, is connected to at least some of the I/O bumps. The IC chip further includes a second circuit to provide electrical connections between the first die and the second die. The display apparatus further comprises a circuit board electrically connected to the input/output bumps of the IC chip and to a power system to provide electrical connections between the power system and each of the first die, the second die, and the LED devices of the IC chip.

[0027] For the rest of the disclosure, a “circuit” can include any structure that can conduct an electrical current or can transmit an electrical potential. A circuit can include, for example, a wire, a via, as well as any passive or active devices (e.g., a resistor, a capacitor, an inductor, a transistor, etc.)

[0028] In some examples, the first die and the second die can be arranged along a lateral direction within the IC chip. The IC chip may include a shoulder structure abutting the first die along the lateral direction. The shoulder structure may include electrical conduction paths that extend across the shoulder structure from the front side of the IC chip to the back side of the IC chip to provide electrical connections between the LED devices and the I/O bumps. The IC chip may include fan-out circuits configured as a front side redistribution layer (RDL) adjacent to the LED devices and on the front side of the IC chip. The front side RDL can extend from the shoulder structure to the first die to provide electrical connections between a first end of the electrical conduction paths and the first die. The first die further includes an inner layer circuit to provide electrical connection between the first end of the electrical conduction paths and the LED devices. The IC chip may also include another front side RDL that extends from the second die over to the first die to provide electrical connections between the first die and the second die.

[0029] Various configurations are proposed to connect a second end of the electrical paths of the shoulder structure to the I/O bumps on the back side of the IC chip. In one example, the I/O bumps can be formed on part of the shoulder structure on the back side of the IC chip to electrically connect to the second end of the electrical conduction paths. In another example, the IC chip may include fan-out circuits configured as a back side RDL opposite to the front side RDL. The I/O bumps can be formed on the backside RDL, and the backside RDL can extend from the I/O bumps to the shoulder structure to provide electrical connections between the I/O bumps and the second end of the electrical conduction paths.

[0030] In some examples, the first die and the second die can form a stack along the vertical direction within the IC chip. The IC chip may include a first shoulder structure abutting the first die along the lateral direction and a second shoulder structure abutting the second die along the lateral direction. The first shoulder structure may include first electrical conduction paths that extend across the first shoulder structure along the vertical direction. The second shoulder structure may include second electrical conduction paths that extend across the second shoulder structure along the vertical direction. The first die may include a first front side RDL adjacent to the LED devices. The first front side RDL extends from the first shoulder structure to the first die to provide electrical connections between the LED devices and the first electrical conduction paths via the first die. In some examples, the first shoulder structure in the first die may be replaced by through silicon vias (TSVs) within the body of the first die itself. The TSVs may be in the perimeter region of the first die or within substantially an entire area of the first die.

[0031] Various configurations are proposed to provide electrical connections between the first shoulder structure and the second shoulder structure. In one example, the first electrical conduction paths and the second electrical conduction paths can be electrically connected together via I/O bumps sandwiched between the first shoulder structure and the second shoulder structure. In some examples, the IC chip may include opposite RDL layers formed on, respectively, a backside of the first die (facing away from the front side of the IC chip) and a front side of the second die facing the backside of the first die. The opposite RDL layers can extend to, respectively, the first shoulder structure and the second shoulder structure to provide electrically connections to, respectively, the first electrical conduction paths of the first shoulder structure and the second electrical conduction paths of the second shoulder structure. The IC chip may include I/O bumps sandwiched between the opposite RDL layers to provide electrical connections between the opposite RDL layers and between the first electrical conduction paths and the second electrical conduction paths. The I/O bumps on the back side of the IC chip can be located on the second shoulder structure, or on another backside RDL that extends over the second chip, as described above.

[0032] Other configurations are also proposed to integrate the LED devices and the dies in an integrated circuit chip. In one example, the IC chip may include a chip carrier to hold the first die and the second die arranged along the lateral direction. The chip carrier may include electrical conduction paths to provide electrical connections to the I/O bumps on the back side of the IC chip. The IC chip may include bridge circuits to provide electrical connections between the LED devices and the electrical conduction paths within the chip carrier. In another example, the IC chip may include the first die and the second die forming a stack along the vertical direction, and each of the first die and the second die may include through silicon vias (TSVs) to provide electrical connections between the LED devices and the I/O bumps on the back side.

[0033] With the disclosed techniques, the LED devices and the control circuits can be integrated in a single integrated circuit chip. Such arrangements can substantially reduce the separation distances between the components of a display system, which reduces not only the form factor of the display system but also the routing distances, and the operation speed of the display system can be improved as a result. The disclosed techniques are particularly advantageous for implementation of a high performance display system in a wearable device (e.g., a head mount display) which has very limited space.

[0034] Examples of the disclosure may include or be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, e.g., a virtual reality (VR), an augmented reality (AR), a mixed reality (MR), a hybrid reality, or some combination and/or derivatives thereof. Artificial reality content may include completely generated content or generated content combined with captured (e.g., real-world) content. The artificial reality content may include video, audio, haptic feedback, or some combination thereof, any of which may be presented in a single channel or in multiple channels (such as stereo video that produces a three-dimensional effect to the viewer). Additionally, in some examples, artificial reality may also be associated with applications, products, accessories, services, or some combination thereof, that are used to, e.g., create content in an artificial reality and/or are otherwise used in (e.g., perform activities in) an artificial reality. The artificial reality system that provides the artificial reality content may be implemented on various platforms, including a head-mounted display (HMD) connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.

[0035] FIG. 1 shows a cross-sectional view of a .mu.LED 100 according to some examples of the present disclosure. As shown in FIG. 1, .mu.LED 100 includes, among others, a substrate 102, a semiconductor epitaxial layer 104 disposed on the substrate 102. Epitaxial layer 104 can be shaped into a mesa 106. An active layer 108, which can include quantum well structures configured to emit light of a pre-determined wavelength range when activated, can be included in mesa 106. Mesa 106 has a truncated top covered by a P-type contact pad 110, whereas a part of epitaxial layer 104 outside of mesa 106 may be covered by an N-type contact pad 112. An electric signal can be applied across P-type contact pad 110 and N-type contact pad 112 to activate active layer 108 to emit light 114. Moreover, mesa 106 also has a near-parabolic shape to form a reflective enclosure. The near-parabolic structure of mesa 106 can be etched directly onto the LED die during the wafer processing steps. Mesa 106 for a typical .mu.LED can have a diameter of about 50 micrometers (.mu.m) or less, whereas each of P-type contact pad 110 and N-type contact pad 112 may have a diameter of about 20 .mu.m.

[0036] Light 114 emitted from active layer 108 can be reflected off the internal walls of mesa 106 toward light emitting surface 116 at an angle sufficient for the light to escape the .mu.LED die 100 (i.e., within an angle of total internal reflection). Light 114 can form a quasi-collimated light beam as the light emerges from light emitting surface 116.

[0037] FIG. 2A and FIG. 2B show an example of a .mu.LED display apparatus 200 according to some examples of the present disclosure. Although the examples of FIG. 2A and FIG. 2B are based on .mu.LED devices, it is understood that the examples of FIG. 2A and FIG. 2B are applicable to other types of LED devices as well. FIG. 2A shows a cross-sectional view of the display apparatus, whereas FIG. 2B shows a top view of the display apparatus. As shown in FIG. 2A, .mu.LED display 200 can include an array of .mu.LED dies 202 including, for example, .mu.LED die 202a, .mu.LED die 202b, and .mu.LED die 202c assembled on a backplane 204.

[0038] Backplane 204 may include a structure for attaching a plurality of .mu.LED dies, to provide electrical connections and structural support for the plurality of .mu.LED devices. As used herein, “backplane” may refer to any structure that provides a surface (which can be planar, curved, etc.) for attaching a plurality of LED devices (which may include .mu.LED devices as described in this disclosure) and for providing electrical signals to the plurality of LED devices. The backplane can be configured as a display backplane to form a display device. For example, the backplane can hold assemblies of LED devices forming display elements, and the backplane may also include traces to provide electrical signals to the LED devices to control the information displayed by the display elements. Backplane 204 may comprise traces, which may connect to other components. Backplane may also comprise electrical contact points, e.g., metal pads, which may provide access to the traces. For example, as shown in FIG. 2A and FIG. 2B, backplane 204 includes electrical traces 206a, 206b, and 206c to electrically connect with, respectively, .mu.LED die 202a, .mu.LED die 202b, and .mu.LED die 202c. Electrical traces 206a, 206b, and 206c allow each of .mu.LED die 202a, .mu.LED die 202b, and .mu.LED die 202c to be individually controlled by applying different signals. Backplane 204 also includes an electrical trace 208 to act as a return current path for each of .mu.LED die 202a, .mu.LED die 202b, and .mu.LED die 202c. Backplane 204 may include different kinds of materials, such as Thin Film Transistor (TFT) glass substrate, polymer, polychlorinated biphenyl (PCB), etc. Although FIG. 2A illustrates that backplane 204 has a rectangular shape, it is understood that backplane 204 can have various shapes and sizes.

[0039] Each of .mu.LED die 202a, .mu.LED die 202b, and .mu.LED die 202c can have a structure similar to .mu.LED die 100 of FIG. 1. Each .mu.LED die in FIG. 2A and FIG. 2B may include substrate 102, epitaxial layer 104, mesa 106, and active layer 108. In addition, each .mu.LED die includes a device-side bump 210 and a device-side bump 212. While FIG. 2A and FIG. 2B illustrate that the bumps are of rectangular shape, it is understood that the bumps can take on other shapes including, for example, rounded shapes, dome shapes, etc. Device-side bump 210 can be connected to P-type contact pad 110 (not shown in FIG. 2A and FIG. 2B), whereas device-side bump 212 can be connected to N-type contact pad 112 (also not shown in FIG. 2A and FIG. 2B). Moreover, backplane 204 includes backplane-side bumps at each location for placing a .mu.LED die. For example, backplane 204 includes backplane-side bumps 214 and 216 for .mu.LED die 202a. Backplane 204 also includes metal pads (not shown in FIG. 2A) which serve as a foundation on which backplane-side bumps 214 and 216 are deposited, and to provide electrical contact to traces 206 and 208. Conductive bonding (e.g., metallic bonding) can be formed between the bumps of the .mu.LED dies and the contacts to provide electrical paths between the .mu.LED die and backplane 204.

[0040] In some examples, .mu.LED display apparatus 200 can be configured as a scanning display in which the LEDs configured to emit light of a particular color are formed as a strip (or multiple strips). For example, as shown in FIG. 2C, a plurality of .mu.LED dies including .mu.LED die 202a, .mu.LED die 202b, and .mu.LED die 202c, etc. can be assembled along an X-axis to form a .mu.LED strip 220 configured to emit green light on backplane 204. In addition, backplane 204 also includes a .mu.LED strip 230 configured to emit red light and an LED strip 240 configured to emit blue light.

[0041] .mu.LED strips 220, 230, and 240, as well as additional strips of red, green and blue .mu.LEDs, can be assembled along a Y-axis as parallel strips on backplane 204 to form a scanning display. FIG. 2D illustrates an example of a scanning display 250 comprising .mu.LED display apparatus 200, a mirror 252, and a lens 254. In scanning display 250, each strip of LEDs can be configured to emit light of a particular color (e.g., one of red, green, or blue). For example, .mu.LED strip 220 can emit green light 260, .mu.LED strip 230 can emit red light 270, etc. The lights can be converged by lens 254 and reflected by mirror 252 into eyeball 256 of a person. To perform sequential scanning, each strip of .mu.LEDs can be controlled to emit light to project a line of pixels of an image onto the retina of eyeball 256. The projection of each line of pixels can be sequential. Through the rotating action of mirror 252, each line of pixels can be projected at different points at different times on the retina, to create the perception of the image.

[0042] In the examples of FIG. 2A-FIG. 2D, backplane 204 has backplane-side bumps for each .mu.LED to transmit control signals to each .mu.LED. Such arrangement, while allowing each .mu.LED to be individually controlled, can lead to a large number of backplane-side bumps being placed on the backplane when the display includes a large number of pixels to improve resolution. For example, if scanning display 250 includes one million .mu.LEDs, one million pairs of backside-bumps 214 and 216 need to be provided on backplane 204 to provide electrical connections to each of the one million .mu.LEDs. Additional wirings 206 and 208 are also needed on backplane 204 to provide electrical connections to the backside-bumps.

[0043] The large number of bumps and the associated wirings can degrade the tight integration between the LED devices and the control circuits. For example, additional backplane spaces may be needed to place the bumps, which can increase the distances between the LED devices and the control circuits. As signals need to travel through longer distances, the operation speeds of both the LED devices and the control circuits can be reduced as a result.

[0044] FIG. 2E illustrates an example of a display device 280 that includes three arrays of LEDs that are coupled to a waveguide. The LEDs may be .mu.LEDs. As shown on the left-hand side of FIG. 2E, the display device 280 may include a first array 281 of LEDs that are configured to emit red light, a second array 282 of LEDs that are configured to emit green light, and a third array 283 of LEDs that are configured to emit blue light. As shown on the right-hand side of FIG. 2E, collimating lenses 284 may be provided to collimate light from each of the arrays 281, 282, and 283 of LEDs. One collimating lens 284 may be provided for each array 281, 282, and 283 of LEDs. Further, a single waveguide 285 may be provided to receive light from the collimating lenses 284 and to direct light toward the user’s eye 286.

[0045] FIG. 2F illustrates an example of a display device 290 that includes three arrays of LEDs that are coupled to a waveguide. The LEDs may be .mu.LEDs. As shown in the top portion of FIG. 2F, display device 290 may include die 291, die 292, and die 293, which are mounted on a backplane 294 via I/O bumps 295. The dies 291, 292, and 293 may be LED dies. Die 291 may include an array of LEDs that are configured to emit red light, such as the first array 281 of LEDs shown in FIG. 2E. Die 292 may include an array of LEDs that are configured to emit green light, such as the second array 282 of LEDs shown in FIG. 2E. Die 293 may include an array of LEDs that are configured to emit blue light, such as the third array 283 of LEDs shown in FIG. 2E. The dies 291, 292, and 293 are configured to be co-planar along the z direction, but may be staggered in any suitable configuration along the x direction and/or the y direction. A first additional layer 297, such as a first fan-out circuit, may be provided between die 291 and the backplane 294. A second additional layer 298, such as a second fan-out circuit, may be provided between die 292 and the backplane 294. A third additional layer 299, such as a third fan-out circuit, may be provided between die 293 and the backplane 294. The backplane 294 may have driver and graphics functions. The backplane 294 may include a backplane die 289 that is positioned underneath at least one of the dies 291, 292, or 293, and that drives the dies 291, 292, and 293.

[0046] The bottom portion of FIG. 2F shows a cross-section taken along line A-A labeled in the top portion of FIG. 2F. As shown in the bottom portion of FIG. 2F, a redistribution layer 296 may be provided to allow the dies 291, 292, and 293 to interface with the backplane die 289 such that the dies 291, 292, and 293 are not required to be positioned entirely or exactly on top of the backplane die 289. Additional I/O bumps 288 may be provided on the underside of the backplane 294 in order to provide a connection between the backplane 294 and a sensor aggregation chip (not shown), and to supply power to the integrated circuit, including the dies 291, 292, and 293.

[0047] FIG. 3 illustrates an example of a display system 300 that can be part of or include .mu.LED display apparatus 200. As shown in FIG. 3, display system 300 includes pixel pipelining circuits 302, driver control circuits 304, driver circuits 306, an array of uLED devices 308, and power system 310. Pixel pipelining circuits 302 can generate pixel data to be rendered by display system 300. Pixel data can include, for example, an image of a virtual reality scene, a composite image of a mixed reality scene, an image captured by a camera, etc. Driver control circuits 304 can generate control signals and data signals for driver circuits 306 based on the pixel data. The control signals can include, for example, address signals to select a uLED device among the array of uLED devices 308. The data signals can set an output intensity of the selected uLED device. Both address signals and data signals can be high speed signals to allow display system 300 to display images at a high resolution and at a high refresh rate. Typically both pixel pipelining circuits 302 and driver control circuits 304 are fabricated using process technologies that support high speed operations and relatively low operation voltages.

[0048] In addition, as shown in FIG. 3, driver circuits 306 may include a set of control drivers 312 to provide the control signals and a set of data drivers 314 to provide the data signals. Driver circuits 306 can receive the address and data signals from driver control circuits 304 and control the output intensities of the uLED devices based on, for example, controlling the currents that flow through the uLED devices based on the data signals. As shown in FIG. 3, driver circuits 306 may include transistors and capacitors controlled by the control signals and data signals to control the flow of current in the uLED devices. Typically driver circuits 306 are fabricated using process technologies that support high operation voltages and relatively low speed operations.

[0049] Power system 310 may include a power supply circuit (e.g., a voltage regulator), as well as other elements (e.g., voltage supply line, ground line, etc.). As shown in FIG. 3, power system 310 can be electrically connected to each of pixel pipelining circuits 302, driver control circuits 304, and driver circuits 306, to, for example, supply electric power (e.g., voltage 320) and/or provide a current return path. Power system 310 also provides a return path 322 for uLED devices 308.

[0050] As described above, it is advantageous to integrate pixel pipelining circuits 302, driver control circuits 304, driver circuits 306, and uLED devices 308 within a single integrated circuit chip to reduce the separation distances between these components. Such arrangements can reduce the form factor of the display system as well as the routing distances and improves the operation speed of the display system.

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