Oculus Patent | Assembly Of Semiconductor Devices

Patent: Assembly Of Semiconductor Devices

Publication Number: 20180269234

Publication Date: 20180920

Applicants: Oculus

Abstract

A method for manufacturing a display element comprising a plurality of pixels, each comprising a plurality of subpixels. The method comprises undertaking, using a pick up tool, a first placement cycle (1908) comprising picking up a plurality of first, untested LED dies and placing them on a display substrate at locations corresponding to the plurality of pixels, testing (1912) the first LED emitters on the display substrate to determine one or more locations of non-functional first LED emitters, selecting one or more second tested LED dies based on a result of the test, configuring the selected one or more second LED dies to enable their pick up and placement on the display substrate and undertaking, using the PUT, a second placement cycle (2008) comprising picking up the selected one or more second LED dies and placing them on the display substrate at the determined locations of the nonfunctional first LED emitters.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional of U.S. patent application Ser. No. 15/753,959, filed Feb. 20, 2018, which is a National Phase application of International Application No. PCT/GB2016/052722, filed Apr. 11, 2016, which claims the benefit of United Kingdom Application No. 201515564.1, filed Sep. 2, 2015, United Kingdom Application No. 201520265.8, filed Nov. 17, 2015, United Kingdom Application No. 201607248.0, filed Apr. 26, 2016, and United Kingdom Application No. 201609422.9, filed May 27, 2016,* each incorporated by reference in its entirety*

TECHNICAL FIELD

[0002] The invention relates to methods and apparatus for assembling semiconductor devices, LED dies for display technologies, displays and methods of manufacture for displays. Specifically, the invention is related to, but need not be limited to, Inorganic Light Emitting Diode (ILED), micro-LED (.mu.LED) dies for display technologies, .mu.LED displays and/or methods of manufacture for .mu.LED displays. The invention may relate to methods and apparatus for assembling semiconductor devices by contact printing.

BACKGROUND

[0003] Displays are ubiquitous and are a core component of wearable devices, smart phones, tablets, laptops, desktops, TVs and display systems. Common display technologies today range from Liquid Crystal Displays (LCDs) to more recent Organic Light Emitting Diode (OLEO) Displays and Active Matrix Organic Light Emitting Diode Displays (AMOLEDs).

[0004] The display architectures include passive and active matrix displays depending on whether each pixel is driven separately or not. Active drive circuitry uses thin film transistor (TFT) technology where transistors based on amorphous silicon (A-Si), low temperature polysilicon (LTPS) and amorphous Indium Gallium Zinc Oxide (IGZO) technology are manufactured on glass panels which may have glass substrate sizes from first generation displays of around 30 cm.times.40 cm to the latest tenth generation displays (known as GEN10) of around 2.88 m.times.3.15 m.

[0005] In most portable devices (i.e. battery powered devices) the display uses a majority of the available battery power. Additionally, the most common user complaint for portable 30 devices is insufficient display brightness. To extend battery life and improve brightness levels it is necessary to develop new display technologies that reduce power consumption and produce higher luminance emission from the light source.

[0006] Inorganic LEDs (ILEDs) are emerging as the third generation of flat display image generators based on superior battery performance and enhanced brightness. The ILED Display is at a basic level a variation of the OLED (organic LED) display. The OLED concept is based on passing current through organic or polymer materials that is sandwiched between two glass planes to produce light. The proposed ILED Display concept essentially replaces the organic LED material with a discrete standard LED (which is made of inorganic materials) at each pixel of the display (each pixel consists of three individual Red, Green and Blue LEDs for colour displays).

[0007] Standard (i.e. inorganic) LED devices have been around for many years and their performance (efficiency, brightness, reliability and lifetime) has been optimised over many years as the LED industry has pursued many commercial opportunities–especially the challenge of developing LED technology to enable it to replace the standard incandescent bulbs for general light applications, i.e. inorganic LEDs are significantly more efficient, bright and reliable than the new and less developed OLED materials.

[0008] The concept of individually switchable standard LEDs (R, G & B) at each pixel in a display is well known. This approach is in widespread use for large information displays. However, to-date it has not been possible to scale this approach down to smaller displays as standard LEDs are typically planar chips which are inefficient for light direction control. Additionally, the assembly of the many millions of pixels needed for a laptop or smart phone display is not feasible at this scale using traditional assembly manufacturing techniques.

[0009] The current challenges with ILED display manufacture are significant and assembly techniques to overcome wafer yields losses need to be factored in to the manufacturing strategy of ILED displays for today’s yields and higher anticipated yields in the future. Selective pick up tools (PUTs) is one solution to overcoming yield problems where defective die are identified and replaced at source. Depending on the yield, it may not be practical or economical either to replace known bad die or to transfer only KGD from a wafer to a temporary carrier for pick to the TFT substrate. Both approaches require wafer level testing to determine KGD or defective chips on the wafer, which is complicated.

[0010] Smart assembly processes with resolutions to manipulate and handle small die improve ILED assembly on the glass panel. There is therefore a need for an assembly process with high throughput that can enable massive parallel pick and transfer of ILED dies of size <10 .mu.m a side from the native LED wafer onto a glass TFT substrate at accuracies approx .+-.3 .mu.m or less.

[0011] Smart assembly methods are being developed in the industry for ILED displays and range from “non selective” elastomer conformal stamps, laser assisted transfer, direct self-assembly methods, fluidic assembly and selective MEMs based printheads. All techniques require the preparation of assembly ready chips where the bulk of the substrate is removed or the epilayer released from the substrate. For ILED displays to become a commercial reality, many or all of the above challenges need to be solved.

SUMMARY

[0012] According to the invention in an aspect, there is provided a method for manufacturing a display element comprising a plurality of pixels, each pixel comprising a plurality of sub-pixels, each sub-pixel being configured to provide light of a given wavelength, the method comprising: undertaking, using a pick up tool, PUT, a first placement cycle comprising picking up a plurality of first, untested LED dies, each first LED die comprising at least one first LED emitter configured to provide one of the plurality of sub-pixels of the display, and placing the first LED dies on a display substrate at locations corresponding to the plurality of pixels of the display; testing the first LED emitters on the display substrate to determine one or more locations of non-functional first LED emitters; from a plurality of second, tested LED dies each comprising at least one second LED emitter configured to provide one of the plurality of sub-pixels of the display, selecting one or more second LED dies based on a result of the test; configuring the selected one or more second LED dies to enable their pick up and placement on the display substrate; and undertaking, using the PUT, a second placement cycle comprising picking up the selected one or more second LED dies and placing the selected one or more second LED dies on the display substrate at the determined locations of the non-functional first LED emitters.

[0013] Untested LED dies encompass LED dies that have not been tested on the wafer during or after fabrication. Untested LED dies may not have any test data associated with them and giving an indication of their operability, save for information relating to wafer yield, wafer material quality and/or the like. Tested LED dies encompass dies that have been tested to determine their operability. Tested LED dies may be those dies that have been tested after fabrication, perhaps on the wafer, and that have been determined to be operable. These LED dies may also be termed Known Good Dies, KGD.

[0014] It is noted that not all LED dies will be testable on the display substrate without further display fabrication steps being undertaken. For example, a vertical LED device, which has electrodes on two opposed surfaces thereof, needs further a metallisation step of the display fabrication process before it can be fully tested, e.g. for short circuit. This makes the second placement cycle much more complicated, if not impossible.

[0015] It is also noted that in exemplary methods, the non-functioning first LED dies are not replaced by the second placement cycle. Rather, in exemplary methods, the second LED dies are placed at the pixel location in addition to the non-functioning first LED dies.

[0016] Optionally, the step of configuring the selected one or more LED dies comprises depositing a deformable material on the one or more selected second LED dies.

[0017] Optionally, the deformable material is configured to cause adhesion between the one or more selected second LED dies and the PUT during the second placement cycle.

[0018] Adhesion may encompass van der Waal forces due to the deformability (or conformability) of the deformable material.

[0019] Optionally, the method the step of depositing the deformable material on the one or more selected second LED dies comprises applying the deformable material to a mould or carrier element and engaging the mould or carrier with a surface of one or more of the plurality of second LED dies so that the deformable material is in contact with the surface of the one or more of the plurality of second LED dies.

[0020] Optionally, depositing the deformable material on the one or more selected second LED dies comprises modifying a level of adhesion between the deformable material and the one or more selected second LED dies so that the deformable material adheres to the one or more selected LED dies.

[0021] Optionally, the step of modifying the level of adhesion between the deformable material and the one or more selected second LED dies comprises irradiating with light one or more portions of the mould or carrier element corresponding to locations of the one or more selected second LED dies. Optionally, the light comprises ultraviolet light.

[0022] Optionally, prior to depositing the deformable layer on the one or more selected second LED dies, the method comprises placing the selected second LED dies on a handle layer. Optionally, the selected second LED dies are adhered to the handle layer.

[0023] Optionally, the second placement cycle comprises modifying a level of adhesion between one or more of the selected second LED dies and the handle layer, such that the level of adhesion is less than a force applied by the PUT.

[0024] Optionally, the method comprises depositing a deformable material on the plurality of first LED dies, prior to undertaking the first placement cycle.

[0025] Optionally, the deformable material is configured to cause adhesion between the plurality of first LED dies and the PUT during the first placement cycle.

[0026] Optionally, the method further comprises undertaking a further test of the first LED emitters and/or the second LED emitters after the second placement cycle to determine locations of one or more non-functional first and/or second LED emitters.

[0027] Optionally, the method further comprises selecting one or more third, tested LED dies after undertaking the further test, based on a result of the further test.

[0028] Optionally, the test and/or the further test comprises applying a reverse bias to the first and/or the second LED emitters and/or applying a forward bias to the first and/or second emitters and using one or more filter(s) to analyse the emission from the first and/or second LED emitters.

[0029] Optionally, the method further comprises undertaking one or more calibration cycles of an assembled display based on the results of the test and/or the further test.

[0030] Optionally, the one or more calibration cycles comprise disconnecting one or more non-functional first and/or second LED emitters from a drive circuitry on the display substrate.

[0031] Optionally, the method further comprises depositing an underfill or non-conductive film on the substrate of the display, prior to the first and/or second placement cycles.

[0032] Optionally, the method further comprises modifying a viscosity of the underfill or non-conductive film to enable pre-bonding or bonding of the first and selected second one or more LED dies to the display substrate.

[0033] Optionally, the first and/or second LED dies comprise a bonding element arranged to permit interconnection of the first and/or second LED dies to the display substrate.

[0034] Optionally, the bonding element is configured to form a temporary contact with an electrical contact of the display substrate, thereby allowing testing of the first and/or second LED dies.

[0035] Optionally, the method comprises bonding the first and/or selected one or more second LED dies to the display substrate using a bonding head.

[0036] Optionally, the bonding head comprises a drum configured to move across the display substrate of the display and apply a force to the first and/or selected one or more second LED dies positioned thereon.

[0037] Optionally, the PUT is a non-selective PUT.

[0038] Optionally, the first and second LED dies comprise .mu.LED dies comprising one or more respective .mu.LED emitters.

[0039] Optionally, each .mu.LED emitter comprises first and second electrodes configured to allow current to pass through the .mu.LED emitter, and wherein the first and second electrodes are positioned on the same surface of the .mu.LED die.

[0040] Optionally, the first and second electrodes are positioned on a surface of the .mu.LED die opposite an emission surface.

[0041] Optionally, the .mu.LED dies comprise a plurality of .mu.LED emitters, each configured to emit light of substantially the same wavelength.

[0042] Optionally, one of the first and second electrodes is common to each of the plurality of .mu.LED emitters.

[0043] Optionally, the method may further comprise one or more further placement cycles comprising picking up a plurality of display elements, such as passive electronics and/or drive electronics, and placing the display elements at appropriate locations for display manufacture.

[0044] According to the invention in an aspect, there is provided a computer program comprising instructions, which when executed on at least one processor, cause the at least one processor to carry out any one of the methods discussed above.

[0045] According to the invention in an aspect, there is provided a carrier containing the computer program above, wherein the carrier is one of an electronic signal, optical signal, radio signal or non-transitory computer readable storage medium.

[0046] As used herein, the term LED is considered to encompass an ILED. Further, the term LED is considered to encompass a .mu.LED, which may also be an ILED.

[0047] It is noted that methods and apparatus disclosed herein relate to LEDs and display manufacture, although they may also relate to photodetector manufacture. In such methods, the term “LED” may be replaced with “photo-sensor”. Further, other elements relating to display and/or detector manufacture, such as passive electronics and/or drive electronics, may also be placed in additional placement cycles.

[0048] Exemplary methods disclosed herein may comprise a method for assembling LEDs on the top of a non-native substrate to form an LED Display. LED displays may comprise ILEDs, which may be .mu.LEDs. The methods disclosed herein may be tailored according to the known yield constraints appreciated by the industry from both wafer yield losses and in-assembly losses.

[0049] Exemplary methods disclosed herein may comprise a combination of non-selective and selective assembly methods using a non-conformal and/or non-selective pick-up tool.

[0050] As used herein, the term Pick up Tool (PUT) encompasses a tool containing a single pick up head or multiple pick up heads. Each head may be designed to pick at least one LED die (for example, a .mu.LED or ILED) from a handle layer (also termed a handle carrier substrate) and place the LED die onto a final substrate, for example a display substrate such as a TFT. This may require LED dies to be manufactured in an assembly ready format. This may require the removal of the bulk substrate from the LED dies. Exemplary methods for removing the bulk substrate may include Laser Lift-off (LLO) for sapphire substrates and/or Etch Stop Layer (ESL) dry/wet etching methods for GaAs substrates.

[0051] A selective PUT may be a tool containing a single pick up head or multiple pick up heads. Each head is individually controllable such that it can be enabled or disabled to pick at least one LED die from a handle carrier substrate selectively. That is, the amount of adherence applied by a selective PUT may be altered, whereby if the pick-up head is enabled then the LED die is picked up, and if the pick-up head is disabled then the LED die is not picked up. The selective PUT may then be configured to place a picked LED die onto a final substrate such as a TFT. A selective PUT may therefore be considered to be programmable depending on the pick-up requirements and is considered an active PUT.

[0052] A non-selective PUT may be a tool containing a single pick up head or multiple pick up heads. The non-selective PUT may be configured to apply a fixed level of adherence to any given LED die. The level of adherence may not be changed. A non-selective PUT may be designed to pick according to a predetermined pattern or sequence. Each head of a non-selective PUT therefore cannot be individually enabled or disabled to pick a single LED die from a handle carrier substrate and place the LED die onto a final substrate such as a TFT. A non-selective PUT may therefore be considered as non-programmable and is considered a passive PUT.

[0053] An ILED display manufacturing approach comprises two features:

1) a spatial map across the wafer (or handle carrier substrate) of Known Good Die (KGD) from a high yielding wafer, which requires wafer level testing prior to assembly; and 2) a selective PUT to pick and place KGD.

[0054] The inventors have appreciated that for an LED (in particular an ILED) display manufacture method, the combination of KGD testing at wafer source coupled with a selective PUT is a significant challenge and not readily achieved. The wafer testing may make this approach economically impractical. Alternative strategies are desirable.

[0055] Exemplary assembly or microassembly methods may be carried out by attaching a transfer device directly to the PUT head. The transfer device may enable the selectivity necessary to pick KGD for microassembly.

[0056] The combination of the PUT and the transfer device may contact the LED die for the pick and the placement of the LED die on the TFT substrate. Examples of transfer devices may comprise conformal transfer devices and/or electrostatic transfer devices. In both cases the transfer device is removed from the element after placement.

[0057] Exemplary methods disclosed herein may have a fine resolution to manipulate and handle small dies and may achieve a high throughput. This may enable, for example, massive parallel pick and transfer of ILED dies of sizes <10 .mu.m a side from the native LED wafer onto a glass TFT substrate at accuracies approx .+-.2 .mu.m or less.

[0058] In exemplary methods disclosed herein a deformable material (forming an intermediate layer) may be deposited on a surface of one or more ILED dies, and a head of a non-conformal pick-up tool (PUT) may be used to contact the deposited deformable material. The upper surface of the intermediate layer contacts the PUT and may cause the ILED dies to adhere to the PUT head through the intermediate layer. The PUT, with a plurality of ILED dies adhered to its head, may direct the chips to a desired position over a glass or plastics thin film transistor panel substrate. Then, the upper surface of intermediate layer may be released from the PUT head so that the intermediate layer and ILED dies remain appropriately located on the receiving substrate. The PUT may be non-conformable. The intermediate layer may be deformable such that it is able to make conformal contact with the ILED dies. The intermediate layer on the ILED dies may enable selection of particular ILED dies, such as selection between defective ILED dies and KGD.

[0059] Disclosed herein are methods of LED (in particular ILED) display manufacture. The methods may lead to yield improvement based on LED emitter redundancy schemes that take into consideration realistic LED wafer starting yields. The methods may include the combination of non-selective and/or selective processes for pick and place assembly cycles.

[0060] For the remainder of this document the exemplary arrangement of .mu.LED dies and are ILEDs is used to describe methods and apparatus for display manufacture. However,* it is noted that the principles of the invention may be applied to other types of LED*

[0061] The methods disclosed herein may include multiple assembly cycles (e.g. pick, place & test) combined with multiple .mu.LED dies per colour per display pixel. Each .mu.LED die may contain multiple .mu.LED emitters to give the same effect as a starting wafer material of high device yield, thereby giving higher display yield. It is noted that a wafer’s device yield relates to the number of functional devices that a wafer may produce and can be affected by a number of factors, such as wafer quality and fabrication methods.

[0062] Display yield encompasses a measure of the number of functional LED emitters or .mu.LED emitters in a display.

[0063] In exemplary methods, a single assembly station, or alternatively multiple assembly substations, may undertake first assembly cycle (cycle A) (e.g. pick, place & test) as follows: [0064] The .mu.LED dies from a wafer containing untested .mu.LED dies (Die Type A) may be deployed; [0065] The .mu.LED dies from the wafer containing untested .mu.LED dies may be post processed to a microassembly readiness state and may be mounted on a temporary handle layer for pick and place; [0066] one or more of the .mu.LED dice may have a deformable material, which may form an intermediate transfer layer, applied thereto when mounted on the temporary handle layer; [0067] A transfer printing non-selective and non-conformal PUT may pick an array of .mu.LED dies from a handle layer. The array of .mu.LED dies may be placed on a display substrate starting, for example, at one corner, and each die corresponding to a pixel location of the display [0068] This sequence may be repeated with the pick location on the handle layer moving sequentially to the next (e.g. adjacent) array of .mu.LED dies and a placement location moving to the next (e.g. adjacent) corresponding set of pixel locations on the substrate–the next square in a chess board pattern, by way of analogy, wherein each square comprises an array of .mu.LED dies; [0069] Each .mu.LED die in each array comprises at least one .mu.LED emitter to provide a sub-pixel of a pixel of the display; [0070] Once the sequence has moved through all the squares in the chess board pattern for one sub-pixel type (i.e. emission colour–RGB), the same process is repeated for the other two sub-pixel types; [0071] Once all sub-pixel types are completed, a test sequence may be undertaken (e.g. all .mu.LED dies are turned on and functionally tested and it is determined which .mu.LED dies and/or emitters in which pixel locations are not working); [0072] The test sequence may undertake a screening of dies using filters to tag and identify one or more die(s) that are outside the parametric performance acceptance limits of the display. [0073] A defect map may be recorded and programmed into the display memory for calibration during a calibration cycle (Cycle C).

[0074] In exemplary methods, a single assembly station, or alternatively multiple assembly substations may undertake a second assembly cycle (cycle B1) (e.g. pick, place & test) as follows: [0075] The .mu.LED dies from a wafer containing untested .mu.LED dies or tested .mu.LED dies, such as KGD, (Die Type B) may be deployed; [0076] The .mu.LED dies from wafer containing untested .mu.LED dies or tested .mu.LED dies may be post processed to a microassembly readiness state and may be mounted on a temporary handle layer for pick and place; [0077] The .mu.LED dies may have a deformable material, which may form an intermediate transfer layer, applied to one or more untested or tested .mu.LED dies when mounted on the temporary handle layer; [0078] The deformable material may be selectively applied to a wafer of untested or tested .mu.LED dies according to the defect map identified during the test in of the first assembly cycle; [0079] A transfer printing non-selectable and non-conformal PUT may pick an array of .mu.LED dies from a handle layer containing the untested or tested LED dies. The array of .mu.LED dies may correspond to the pixel locations where non-functioning .mu.LED dies are located after the first placement cycle. The array of .mu.LED dies may be placed on a display substrate starting, for example, at one corner; [0080] Only .mu.LED dies including an intermediate layer may be picked by the PUT; [0081] This sequence is repeated with the pick location on the handle layer moving sequentially to the next (e.g. adjacent) array of .mu.LED dies and a placement location moving to the next (e.g. adjacent) set of locations on the substrate–the next square in a chess board pattern, by way of analogy; [0082] Once the sequence has moved through all the squares in the chess board pattern for one sub-pixel type, the same process may be repeated for the other two sub-pixel types; [0083] Once all sub-pixel types are completed, a test sequence may be undertaken (i.e. all .mu.LED dies are turned on and functionally tested and it is determined which .mu.LED dies and/or emitters in which pixel locations are not working); [0084] The test sequence may undertake a screening of die using filters to tag and identify die which are outside the parametric performance acceptance limits of the display. [0085] A defect map may be recorded and programmed into the display memory for calibration during a calibration cycle (Cycle C).

[0086] In exemplary methods, a single assembly station or an alternative assembly station may undertake a third assembly cycle (Cycle B2), which may be the same as the second assembly cycle (Cycle B1) other than the selection map for .mu.LED pick may generated from the defective map which was determined during the second assembly cycle (Cycle B1). As many subsequent cycles may be undertaken as necessary to achieve a desired display yield.

[0087] Exemplary methods may be based on a redundancy model and not on any physical wafer repair strategy. Alternatively, redundancy strategies may comprise placement of a sister .mu.LED sub-pixel adjacent to a defective sub-pixel. A laser trim function may be deployed to open or melt fuses to disconnect the first .mu.LED from the driving circuit.

[0088] This physical approach to correcting defective sub-pixels while attractive may not be economical in scale when the LED wafer yields are <99%. For example a 90% wafer yield would incur -31K laser trim functions after the first assembly cycle, which may be uneconomical. In addition, a second sub-pixel alone may be insufficient for correction unless the assembly yield for the second placement cycle is guaranteed to be 100%.

[0089] Exemplary methods may comprise a calibration cycle (Cycle C) of the final display based on the defective maps generated during the assembly sequence (cycles A, B1 and optionally B2). The calibration cycle may comprise a laser trim function to isolate from the drive circuitry defective sub-pixels that were identified in the placement cycles leaving the working .mu.LED sub-pixels placed during the placement cycles still connected to the drive circuitry. Electrical repair strategies may be used to isolate from the drive circuitry defective .mu.LED dies identified after the first placement cycle.

[0090] Exemplary methods may comprise one or more of the following features: [0091] The overall target for the .mu.LED wafer yield may be known [0092] The multiple .mu.LED dies per colour per display pixel may be sourced from different locations of the same wafer or from different wafers [0093] The sequence of pick, place & test may be repeated until there is a working .mu.LED die of each colour (R, G and B) in all or nearly all (e.g. 99% or more) or all of the display pixel locations. [0094] The .mu.LED dies may have all contacts on the same side, and the contacts may be placed down onto the glass, enabling the .mu.LED emitters of each .mu.LED die to be powered from the glass substrate immediately after placement. [0095] The methods may be used where the .mu.LED wafer has not been previously tested and a defined number of .mu.LED (single emitter or multi emitter LED) dies are placed per colour per pixel.

[0096] When a .mu.LED die comprises multiple emitters instead of a single emitter, modelling shows that such multiple emitter dies can significantly reduce the number of cycles/dies required per pixel to obtain an acceptable display yield. This can have a significant impact on wafer material used (number of dies required) and assembly time (number of assembly cycles).

[0097] Exemplary methods of the test sequence may comprise one or more of the following features: [0098] Once all sub-pixel types are completed or between each sub-pixel type placement sequence, the .mu.LED die may pre-bonded or final bond in order to carry out in-line panel testing between cycles. A pre-bond state may be a temporary metal to metal contact between the contacts of the .mu.LED die and contact pads on the substrate of the display. This may not be a permanent bond but may be sufficient to allow testing to occur. A final bond may be where the contacts of the .mu.LED die have undergone, for example, reflow (e.g. eutectic) or metallic interdiffusion e.g. Solid Liquid Intediffiusion (SLID) to create a permanent contact. This may involve an excitation source, such as thermal, compression or ultrasonic forces, to ensure a reliable permanent bond. [0099] To aid with the pick and place cycle and also the quality of the interconnection pre-applied underfills or post applied underfills may be applied to ensure a good quality reliable bonding interface. A pre-applied underfill may help with the release of the PUT from the intermediate layer and/or the contacts of the .mu.LED die during placement.

[0100] Exemplary methods for the deposition of the deformable material to the .mu.LED used in the first assembly cycle (Cycle A) may include one or more of the following Spin coating and lithography, spray coating, microcontact printing, lamination and micromoulding.

[0101] Exemplary methods for the deposition of the deformable material to the .mu.LED used in the second or third assembly cycle (Cycle B1 or B2) may include one or more of the following: Inkjet processing and micromoulding.

[0102] Exemplary methods for the application of underfill to the .mu.LED used in the first assembly cycle (Cycle A) may include one or more of the following: Spin coating and lithography, micromoulding and microprinting.

[0103] In exemplary methods an underfill may be applied during bonding. The underfill may comprise a pre-applied B-stage epoxy.

[0104] In exemplary methods a thermocompression bonding process, e.g. C2, may be used.* The bonding process may use CuSn to Cu or Cu to Cu ultra-fine pitch microbump technology*

[0105] Exemplary methods may comprise a hybrid assembly method, which may overcome the constraints and challenges of the current technology Exemplary methods may comprise a sequence of assembly cycles. The sequence of assembly cycles may comprise non-selective and/or selective assembly cycles. The sequence of assembly cycles may comprise a wafer test and/or an in-line panel test. This approach may be enabled by LED dies disclosed herein, which may allow for in-line testing during assembly.

[0106] Methods may comprise a first placement cycle (Cycle A). The first placement cycle may part of the non-selective assembly cycle and/or may use LED dies which have not been tested, e.g. individually tested, at wafer level.

[0107] Methods may comprise a second and/or third placement cycles (Cycles B1, B2). The second and/or third placement cycles may be part of a selective assembly cycle and/or may use LED dies which have been tested e.g. individually tested.

[0108] There may be no LED wafer test before the first assembly cycle (cycle A). The first assembly cycle may only comprise picking and placing of the .mu.LEDs. There may be a LED wafer test before the second and/or third assembly cycles (Cycles B1 and/or B2).

[0109] In exemplary methods, there may be an inline LED die test when placed on the panel between all placement cycles. The probability of each display pixel working is sufficiently high after three placement cycles of the defined number of .mu.LED dies per pixel that it is now possible to obtain working products (displays) with a sufficiently low numbers of defects per display product that a manufacturing line repair strategy can be deployed, i.e. the display yield is sufficiently high that it is considered a manufacturable process. This approach will give zero number of defects per display product for small displays, i.e. the cost increase due to multiple dies per pixel is immaterial for displays of small pixel numbers such as wearable technologies. This approach can be extended to large displays.

[0110] Subsequent .mu.LED dies (after the first placement) may be single emitter .mu.LED dies. This will reduce the size of the .mu.LED dies that are used and reduce the cost.

[0111] Testing between each pick and place cycle may be used to identify defective, non-optimally performing .mu.LED die or missing die as a result of die manufacture or assembly yields and substitute them with a working die at a redundant site located next to the defect .mu.LED die. The working die is taken from a wafer bank of KGD which has been designated for repair work.

[0112] Optionally, a laser is used to cut the tracks for any emitter within a die that are placed but are defective and/or for excess emitters. Multiple but different numbers of LED emitters per pixel working in parallel may create image artefacts, which may not be acceptable.

[0113] A selectable PUT may also be used to repair a LED wafer or handle layer to get a virtual wafer yield of 100% before submitting the wafer to the assembly processes described above. A selectable PUT may be used to repair defects on a LED wafer or handle layer to produce LED wafers or handle layers having a -100% virtual yield.

[0114] In addition to an AOI approach to inspect LEDs, such as .mu.LEDs, (functional, optical power, beam profile) an additional approach may be used, such as reverse biasing the LED and shining light onto it, i.e. getting it to act as a photodiode, and using the behaviour of the LED in photodiode mode to predict and characterise the LEDs parametric performance.

[0115] According to the invention in an aspect, there is provided a method for moving a semiconductor chip, the method comprising: contacting a pick up tool, PUT, head with a surface of a semiconductor chip at a first location, wherein the surface of the semiconductor chip comprises a deformable material configured to adhere to the PUT on contact; moving the PUT to a second location and releasing the semiconductor.

[0116] Optionally, the deformable material comprises an elastic material.

[0117] Optionally, the elastic material comprises an elastomeric material.

[0118] Optionally, the deformable material comprises a structured surface for contacting the PUT head and configured facilitate adhesion and/or release of the semiconductor chip.

[0119] Optionally, the structured surface comprises elongate pillars extending from the surface.

[0120] Optionally, the contact between the PUT head and the deformable material results in substantially no voids therebetween.

[0121] Optionally, the method further comprises depositing the deformable material on a surface of the semiconductor chip.

[0122] Optionally, the method further comprises removing the deformable material from the surface of the semiconductor chip.

[0123] Optionally, removal of the deformable material is by a process of etching. Optionally, the removal of the deformable material is by one of dissolving the deformable material or washing the deformable material away using a solution.

[0124] Optionally, the deformable material is deposited on top of a sacrificial layer deposited on the surface of the semiconductor chip, and wherein the etching process etches away the sacrificial layer.

[0125] Optionally, the PUT head is substantially rigid and/or substantially planar.

[0126] Optionally, method further comprises selectively adhering the PUT head to one or more of a plurality of semiconductor chips.

[0127] Optionally, there are a plurality of semiconductor chips, the method further comprising selectively removing the deformable material from one or more semiconductor chips before contact with the PUT head such that the PUT head does not adhere to those semiconductor chips.

[0128] Optionally, the method further comprises adhering the PUT head to a plurality of semiconductor chip.

[0129] Optionally, the semiconductor chips comprise ILED and/or .mu.LED chips.

[0130] Optionally, the second location is a substrate of a semiconductor device.

[0131] Optionally, the substrate comprises a glass or plastics thin film transistor panel.

[0132] Optionally, the method further comprises arranging a plurality of ILED and/or .mu.LED chips on the substrate to form an image generator of a display.

[0133] According to the invention in another aspect, there is provided a method for forming an image generator of an LED display, the method comprising: depositing a deformable material on a surface of a plurality of ILED and/or .mu.LED chips; contacting a pick up tool, PUT, head with the deformable material deposited on one or more of the plurality of ILED and/or .mu.LED chips, such that the one or more of the plurality of ILED and/or .mu.LED chips adheres to the PUT head; moving the PUT head such that the one or more ILED and/or .mu.LED chips are positioned such that contacts of the one or more ILED and/or .mu.LED chips are in electrical communication with pads of thin film transistors of a glass or plastics thin film transistor panel; and releasing the one or more ILED and/or .mu.LED chips from the PUT head.

[0134] According to the invention in another aspect, there is provided an image generator for an LED display, comprising: a plurality of ILED and .mu.LED chips arranged on a glass or plastics thin film transistor panel, wherein the one or more ILED and/or .mu.LED chips have been arranged on the glass or plastics thin film transistor panel by: depositing a deformable material on a surface of the plurality of ILED and/or .mu.LED chips; contacting a pick up tool, PUT, head with the deformable material deposited on one or more of the plurality of ILED and/or .mu.LED chips, such that the one or more of the plurality of ILED and/or .mu.LED chips adheres to the PUT head; moving the PUT head such that the one or more ILED and/or .mu.LED chips are positioned such that contacts of the one or more ILED and/or .mu.LED chips are in electrical communication with pads of thin film transistors of a glass or plastics thin film transistor panel; and releasing the one or more ILED and/or .mu.LED chips from the PUT head.

[0135] According to the invention in another aspect, there is provided a method for moving a semiconductor chip, the method comprising: contacting a pick up tool, PUT, head with a surface of a semiconductor chip at a first location, wherein the surface of the semiconductor chip comprises an intermediate layer that is conformal and results in a conformal surface contact between the surface of the intermediate layer and the PUT head.

BRIEF DESCRIPTION OF THE DRAWINGS

[0136] FIG. 1 is a schematic cross section of a .mu.LED;

[0137] FIG. 2 is a schematic view of an exemplary .mu.LED die;

[0138] FIG. 3 is a schematic view of an exemplary .mu.LED die;

[0139] FIG. 4 is a section through an exemplary display;

[0140] FIG. 5 is a schematic view an exemplary display manufacturing method;

[0141] FIG. 6 is a schematic view of an exemplary .mu.LED die design;

[0142] FIG. 7 is a schematic cross section of an exemplary .mu.LED;

[0143] FIG. 8(a) is a schematic cross section of an exemplary .mu.LED;

[0144] FIG. 8(b) is a schematic cross section of an exemplary .mu.LED after substrate removal;

[0145] FIG. 9 is a schematic view of an exemplary substrate removal process;

[0146] FIG. 10 is a schematic view of an exemplary substrate removal process;

[0147] FIG. 11 is a schematic view of an exemplary non-selective deformable layer deposition process;

[0148] FIG. 12 is a schematic view of an exemplary selective deformable layer deposition process;

[0149] FIG. 13 is a schematic view of an exemplary selective deformable layer deposition process;

[0150] FIG. 14(a) is a schematic view of an exemplary non-selective pick up process;

[0151] FIG. 14(b) is a schematic view of an exemplary selective pick up process;

[0152] FIG. 15(a) is a schematic view of an exemplary non-selective pick up process;

[0153] FIG. 15(b) is a schematic view of an exemplary selective pick up process;

[0154] FIGS. 16(a) to 16(d) are schematic views of part of an exemplary display;

[0155] FIG. 17 is a schematic view of exemplary .mu.LED dies;

[0156] FIG. 18 is a table of exemplary display yields;

[0157] FIG. 19 is a flow diagram;

[0158] FIG. 20 is a flow diagram;

[0159] FIG. 21 is a flow diagram;

[0160] FIG. 22 is section through an exemplary TFT layer;

[0161] FIG. 23 is a schematic view of an exemplary bonding process;

[0162] FIG. 24 is a schematic view of an exemplary bonding process;

[0163] FIG. 25 shows a beam profile output from a commercial planar LED device and from .mu.LED devices

[0164] FIG. 26 shows an exemplary assembly process flow;

[0165] FIG. 27 shows an exemplary assembly process flow;* and*

[0166] FIG. 28 shows an exemplary assembly process flow.

DETAILED DESCRIPTION

[0167] The inventors have appreciated that ILED Displays may provide future generations of flat display image generators providing superior battery performance and enhanced brightness. The ILED Display is at a basic level a variation of the OLEO display. The OLEO concept is based on passing current through organic or polymer materials that are sandwiched between two glass planes to produce light.

[0168] ILED display manufacture refers to the assembly of semiconductor inorganic light emitting diode (ILED) or other microLED devices onto flexible substrates or substrates such as TFT glass substrates. The assembly of millions of small .mu.LEDs chips to create an ILED display can create unique challenges, for example, when considering wafer and assembly yield losses and the test strategy during in-line assembly onto non-native substrates.

[0169] The inventors have further appreciated some challenges with ILED display manufacture, as set out below.

[0170] High LED wafer yields greater than or equal to 99.99% are ideally preferred for ILED display manufacture because the display industry takes a zero tolerance approach to pixel defects in a display. State of the art LED wafer manufacturing yields vary in the industry considerably depending on the product. A wafer yield >99.9% is considered unrealistic and is one of the primary obstacles to ILED Display manufacture given that the pixel count in displays range from 10 s of thousands for wearable displays to 10s of millions for large area high resolution displays. Alternative strategies are needed which take into consideration existing wafer yield scenarios.

[0171] The dimensions of LED dies required for ILED Displays are significantly smaller in scale compared to standard LED dies for traditional luminaire/lighting applications. The means that traditional assembly methods are not compatible with these chips sizes and therefore finer placement solutions are needed. Specifically, smart assembly processes with resolutions to manipulate and handle small die improve ILED assembly on the glass panel. There is therefore a need for an assembly process with high throughput that can enable massive parallel pick and transfer of ILED dies of size <10 .mu.m a side from the native LED wafer onto a glass TFT substrate at accuracies approximately below .+-.2 .mu.m or less.

[0172] Strategies for assembly include wafer repair where known bad die are replaced on the wafer with KGD die or the transfer of only KGD from the wafer to a temporary carrier for pick to the TFT substrate. Both approaches require complicated wafer probe card testing to determine KGD to generate a defect map on the wafer. These are considered uneconomical and redundant by the methods disclosed herein. Depending on the wafer yield,* it may also not be practical or economical to either replace known bad die or transfer only KGD from a wafer to a temporary carrier for pick to the TFT substrate*

[0173] Smart assembly methods are being developed in the industry for ILED displays and range from “non-selective” elastomer conformal stamps, laser assisted transfer, direct self-assembly methods, fluidic assembly and selective MEMs based print heads. All techniques require the preparation of assembly ready chips where the bulk of the substrate is removed or the epilayer released from the substrate.

[0174] Non-selective pick and place assembly methods may only practical for small display sizes and where die and assembly yields after a first pick and place on the display are greater than 99.99%. As an example, a wearable 320.times.320 pixel display format consists of 307,200 subpixels with 102,400 subpixels of each primary colour red, green. A yield of >99.99% results in 308 defective pixels which require replacement and repair. Replacement and repair strategies at these numbers can be time consuming and not economical for a wearable cost of goods. Alternative lower cost methods are needed.

[0175] Selective pick and place assembly may be a preferred solution in overcoming yields problems where the PUT only selects known good die (KGD) for assembly. This requires full wafer test capability where defective die are identified and a defective wafer map is established.

[0176] The inventors have appreciated that for ILED Displays to become a commercial reality, all of the above challenges may need to be solved. A manufacturing methodology is disclosed herein, which may address the specific needs of the ILED display industry and may overcome one or more shortfalls in existing technologies, such as low wafer yields, complicated wafer test methods and/or selective PUT tool design. Exemplary methods and apparatus disclosed herein may comprise a redundancy scheme. Exemplary methods and apparatus disclosed herein may use micro LEDs (.mu.LEDs) for implementation in display, which may include displays ranging from wearable displays to larger laptop displays.

[0177] Generally, disclosed herein is a method for manufacture of displays. Exemplary displays may be used in display applications, such as a wearable display incorporating .mu.LEDs.

[0178] As used herein, “.mu.LED” technology encompasses micron size ILED devices that directionalise the light output and maximise the brightness level observed by the user. The .mu.LED is disclosed in U.S. Pat. No. 7,518,149 and is a next generation ILED technology developed specifically to deliver directionalised light. As used herein, “directionalised light” encompasses collimated and quasi-collimated light. For example, directionalised light may be light that is emitted from a light generating region of an ILED and at least a portion of the emitted light is directed into a beam having a half angle. This may increase the brightness of the ILED in the direction of the beam of light.

[0179] A .mu.LED may have a circular cross section, in which case a diameter of the .mu.LED is typically less 20 .mu.m. A .mu.LED may have a parabolic structure etched directly onto the ILED die during the wafer processing steps. The parabolic structure may comprise a light emitting region of the .mu.LED and reflects a portion of the generated light to form a quasi-collimated light beam emerging from the chip.

[0180] FIG. 1 shows an exemplary .mu.LED 100. The .mu.LED 100 shown in Figure is the same or similar to that proposed in WO2004/097947 (also published as U.S. Pat. No. 7,518,149) having a high extraction efficiency and outputting quasi-collimated light because of the parabolic shape. A substrate 102 has a semiconductor epitaxial layer 104 located on it. The epitaxial layer 104 is shaped into a mesa 106. An active (or light emitting) layer 108 is enclosed in the mesa structure 106. The mesa 106 has a truncated top, on a side opposed to a light transmitting or emitting face 110 of the .mu.LED 100. The mesa 106 also has a near-parabolic shape to form a reflective enclosure for light generated within the .mu.LED 100. The arrows 112 show how light emitted from the active layer 108 is reflected off the internal walls of the mesa 106 toward the light exiting surface 110 at an angle sufficient for it to escape the .mu.LED device 100 (i.e. within an angle of total internal reflection).

[0181] The parabolic shaped structure of the .mu.LED 100 results in a significant increase in the extraction efficiency of the .mu.LED 100 into low illumination angles when compared to unshaped or standard LEDs.

[0182] FIG. 2 shows an exemplary .mu.LED die 200. The die 200 comprises a single emitter 202 with a “p” electrode 204 and an “n” electrode 206 formed on the same side of the die 200 as a mesa 208. The light is output from a light emitting surface 210 on the opposite side of the .mu.LED die 200 to the electrodes. The light is emitted through the epitaxial layer of the .mu.LED die 200.

[0183] FIG. 3 shows a perspective view of a .mu.LED die 300 comprising a plurality of emitters 302a, 302b. The single die 300 of FIG. 3 comprises two .mu.LEDs. As used herein, the term “single die” encompasses a single and discrete section of substrate, e.g. a semiconductor substrate, on which semiconductor devices are fabricated. The die 300 comprises an n electrode 304 and a p electrode 306a, 306b for each .mu.LED emitter 302a, 302b.

[0184] The size of the .mu.LED die 300 is larger than the die 200 shown in FIG. 3, as the number of .mu.LED emitters is increased. However, in the case where multiple emitters are required and the n and p electrode formations are on the same side of the chip, the real estate used by the die 300 is reduced. For example, if two emitters are required, the die 300 represents a real estate saving in excess of 25% compared to two dies 200, which comprise a single emitter.

[0185] An advantage of apparatus disclosed herein is the interconnect configuration of the dies (i.e. p and n electrodes on an opposite side to the light emitting side). This configuration allows integrated testing of the dies 300 immediately after assembly onto a glass (or other transparent material) panel and before completion of a final display stack assembly. The manufacturing test strategy is therefore simplified and testing can be integrated into the assembly process. It will be appreciated that the interconnect configuration may also permit a simplified die repair or replacement strategy, which may be integrated into the assembly process.

[0186] FIG. 4 is a cross section through a section of a display 400. The display 400 comprises a plurality of .mu.LED dies 402 mounted on a glass top layer 404 such that emission of light is into and through the glass top layer 404. In the exemplary configuration of FIG. 4, both the p and n electrodes 406, 408 are mounted on the same side of each die 402 and on an opposite face of the die 402 to the output face. FIG. 4 shows how the .mu.LED dies 402 may be mounted on TFT layers 410 of the display 400.

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